Architecture
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Figure 2-28. PIC Diagram
PIOA
TD
OPOS1
ONEG1
IOLT0
Tristate
Register
Block
OPOS0
OPOS2*
ONEG0
ONEG2*
PADA
“T”
IOLD0
Output
Register
Block
sysIO
Buffer
QNEG0*
QNEG1*
QPOS0*
QPOS1*
INCK**
INDD
INFF
IPOS0
IPOS1
DI
Input
Register
Block
Control
Muxes
CLK1
CEO
CLK
CE
LSR
GSRN
LSR
GSR
ECLK1
CLK0
CEI
ECLK2
DDRCLKPOL*
DQSXFER*
PADB
“C”
PIOB
*Signals are available on left/right/bottom edges only.
** Selected blocks.
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-28.
The PAD Labels “T” and “C” distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right
edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as inputs.
2-30
LATTICE [ LATTICE SEMICONDUCTOR ]
