Architecture
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LatticeECP2/M DSP Performance
Table 2-11 lists the maximum performance in millions of MAC operations per second (MMAC) for each member of
the LatticeECP2/M family.
Table 2-11. DSP Performance
DSP Performance
Device
ECP2-6
DSP Block
GMAC
3
6
3.9
ECP2-12
ECP2-20
ECP2-35
ECP2-50
ECP2-70
ECP2M20
ECP2M35
ECP2M50
ECP2M70
ECP2M100
7.8
7
9.1
8
10.4
23.4
28.6
7.8
18
22
6
8
10.4
28.6
31.2
54.6
22
24
42
For further information about the sysDSP block, please see the list of additional technical information at the end of
this data sheet.
Programmable I/O Cells (PIC)
Each PIC contains two PIOs connected to their respective sysI/O buffers as shown in Figure 2-28. The PIO Block
supplies the output data (DO) and the tri-state control signal (TO) to the sysI/O buffer and receives input from the
buffer. Table 2-12 provides the PIO signal list.
2-29
LATTICE [ LATTICE SEMICONDUCTOR ]
