Architecture
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
IPexpress™
The user can access the sysDSP block via the ispLEVER IPexpress tool, which provides the option to configure
each DSP module (or group of modules) or by direct HDL instantiation. In addition, Lattice has partnered with The
MathWorks® to support instantiation in the Simulink® tool, a graphical simulation environment. Simulink works with
ispLEVER to dramatically shorten the DSP design cycle in Lattice FPGAs.
Optimized DSP Functions
Lattice provides a library of optimized DSP IP functions. Some of the IP cores planned for the LatticeECP2/M DSP
include the Bit Correlator, Fast Fourier Transform, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/
Decoder, Turbo Encoder/Decoder and Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest
list of available DSP IP cores.
Resources Available in the LatticeECP2/M Family
Table 2-9 shows the maximum number of multipliers for each member of the LatticeECP2/M family. Table 2-10
shows the maximum available EBR RAM Blocks in each LatticeECP2/M device. EBR blocks, together with Distrib-
uted RAM can be used to store variables locally for fast DSP operations.
Table 2-9. Maximum Number of DSP Blocks in the LatticeECP2/M Family
Device
ECP2-6
DSP Block
9x9 Multiplier
18x18 Multiplier
36x36 Multiplier
3
6
24
48
12
24
28
32
72
88
24
32
88
96
168
3
6
ECP2-12
ECP2-20
ECP2-35
ECP2-50
ECP2-70
ECP2M20
ECP2M35
ECP2M50
ECP2M70
ECP2M100
7
56
7
8
64
8
18
22
6
144
176
48
18
22
6
8
64
8
22
24
42
176
192
336
22
24
42
Table 2-10. Embedded SRAM in the LatticeECP2/M Family
Total EBR SRAM
(Kbits)
Device
ECP2-6
EBR SRAM Block
3
55
ECP2-12
ECP2-20
ECP2-35
ECP2-50
ECP2-70
ECP2M20
ECP2M35
ECP2M50
ECP2M70
ECP2M100
12
221
15
277
18
332
21
387
60
1106
1217
2101
4147
4534
5308
66
114
225
246
288
2-28
LATTICE [ LATTICE SEMICONDUCTOR ]
