Architecture
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
By combining input blocks of the complementary PIOs and sharing some registers from output blocks, a gearbox
function can be implemented, which takes a double data rate signal applied to PIOA and converts it as four data
streams, IPOS0A, IPOS1A, IPOS0B and IPOS1B. Figure 2-29 shows the diagram using this gearbox function. For
more information about this topic, please see information regarding additional documentation at the end of this
data sheet.
The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-
quate timing when data is transferred from the DQS to the system clock domain. For further information about this
topic, see the DDR Memory section of this data sheet.
Figure 2-29. Input Register Block for Left, Right and Bottom Edges
INCK**
To DQS Delay Block**
DI
(From sysIO
Buffer)
INDD
SDR & Sync
Registers
DDR Registers
Clock Transfer Registers
IPOS0A
Fixed Delay
0
1
0
1
D0
D2
Q
D
Dynamic Delay
D
QPOS0A
Q
D-Type
/LATCH
Q
D
D-Type*
DEL [3:0]
D-Type
From
Routing
IPOS1A
D1
Q
D
Q
D
QPOS1A
Q
D
Q
D
D-Type
/LATCH
Delayed
DQS
D-Type
D-Type
D-Type*
0
1
To
Routing
CLK0 (of PIO A)
DDRCLKPOL
CLKA
True PIO (A) in LVDS I/O Pair
Comp PIO (B) in LVDS I/O Pair
INCK**
To DQS Delay Block**
INDD
DDRSRC
D0
DI
(From sysIO
Buffer)
SDR & Sync
Registers
DDR Registers
Clock Transfer Registers
0
1
Fixed Delay
IPOS0B
0
1
0
Dynamic Delay
Q
D
Q
D
QPOS0B
D
Q
1
D-Type
/LATCH
DEL [3:0]
D-Type*
D-Type
From
Routing
IPOS1B
0
1
D1
Q
Q
QPOS1B
D
D
D
Q
D
Q
D2
D-Type
/LATCH
D-Type
D-Type
D-Type*
Delayed
DQS
0
1
To
Routing
CLK0 (of PIO B)
Gearbox Configuration Bit
DDRCLKPOL
CLKB
Note: Simplified version does not
show CE and SET/RESET details
*Shared with output register
**Selected PIO.
2-32
LATTICE [ LATTICE SEMICONDUCTOR ]
