Architecture
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
one clock is selected for each input register, pipeline register and output register. Similarly Clock enable (CE) and
Reset (RST) are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3)
at each input register, pipeline register and output register.
Signed and Unsigned with Different Widths
The DSP block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. For
unsigned operands, unused upper data bits should be filled to create a valid x9, x18 or x36 operand. For signed
two’s complement operands, sign extension of the most significant bit should be performed until x9, x18 or x36
width is reached. Table 2-8 provides an example of this.
Table 2-8. Sign Extension Example
Unsigned
9-bit
Unsigned
18-bit
Two’s Complement
Signed 9 Bits
Two’s Complement
Signed 18 Bits
Number Unsigned
Signed
0101
+5
-6
0101
N/A
000000101
N/A
000000000000000101
N/A
000000101
111111010
000000000000000101
111111111111111010
1010
OVERFLOW Flag from MAC
The sysDSP block provides an overflow output to indicate that the accumulator has overflowed. When two
unsigned numbers are added and the result is a smaller number than the accumulator, “roll-over” is said to have
occurred and an overflow signal is indicated. When two positive numbers are added with a negative sum and when
two negative numbers are added with a positive sum, then the accumulator “roll-over” is said to have occurred and
an overflow signal is indicated. Note that when overflow occurs the overflow flag is present for only one cycle. By
counting these overflow pulses in FPGA logic, larger accumulators can be constructed. The conditions overflow
signals for signed and unsigned operands are listed in Figure 2-27.
Figure 2-27. Accumulator Overflow/Underflow
000000011
000000010
000000001
000000000
3
2
1
0101111100
0101111101 253
252
Carry signal is generated for
one cycle when this
254
255
256
0101111110
0101111111
1010000000
0
boundary is crossed
111111111
111111110
111111101
511
510
509
1010000001 257
1010000010
258
Unsigned Operation
000000011
+3
+2
+1
0
-1
-2
-3
0101111100
0101111101 253
0101111110
0101111111
252
000000010
000000001
000000000
111111111
111111110
111111101
Overflow signal is generated
for one cycle when this
boundary is crossed
254
255
1010000000
1010000001
1010000010
-256
-255
-254
Signed Operation
2-27
LATTICE [ LATTICE SEMICONDUCTOR ]
