Specifications ispLSI 8840
Figure 3. ispLSI 8000 Macrocell Overview
Bus Input From Tristate
Bus Track*
Single PT
Feedback to AND Array
PTSA
D
Q
To Big Fast Megablock
or Global Interconnect
PTSA Bypass
PT Clock
Clk En
Global Clock Enable
To Specific
Global Tristate Bus*
Global Clock 0
Global Clock 1
Global Clock 2
R/L
P
From Macrocell
9 or 10
R
PT Reset
Macrocells 0-8
and 11-19
GRST
PT Preset
GRST
Reset pin
To All Macrocells and I/O Cells
Preset/Reset Input has Global Polarity Control
From PT80
2
*Not available for Macrocells 9 and 10.
: Function Selector (E Cell Controlled)
6