Specifications ispLSI 8840
Figure 6. Boundary Scan Register Circuit for I/O Pins
HIGHZ
EXTEST
PROG_MODE
SCANIN
(from previous
cell)
TOE
BSCAN
Registers
BSCAN
Latches
Normal
Function
OE
0
1
D
D
D
Q
Q
Q
D
Q
EXTEST
PROG_MODE
Normal
0
1
Function
I/O Pin
D
Q
SCANOUT
(to next cell)
Shift DR
Clock DR
Update DR
Reset*
*Internal power-up reset signal. Not connected to external reset pin.
Figure 7. Boundary Scan Register Circuit for Input-Only Pins
Input Pin
SCANOUT
(to next cell)
SCANIN
D
(from previous
cell
Q
Shift DR
Clock DR
9