Specifications ispLSI 8840
Figure 2. ispLSI 8000 GLB Overview
I/O Big Fast Megablock Input Tracks
General Purpose Big Fast Megablock Input Tracks
AND Array Input
Routing
Feedback Inputs
43
20
0
Product Term
Sharing Array
Macrocell 0
PT 0
PT 1
PT 2
PT 3
From PTSA
PTSA Bypass
Single PT
To Interconnect
PT Clock
PT Preset
0
PT Reset
Shared PT Clock
Bus Input
From Tristate
Bus Track
PT 4
PT 5
PT 6
PT 7
Macrocell 1
From PTSA
PTSA Bypass
Single PT
To Interconnect
PT Clock
PT Preset
1
PT Reset
Shared PT Clock
Bus Input
From Tristate
Bus Track
Macrocell 2
PT 8
PT 9
PT 10
PT 11
From PTSA
PTSA Bypass
Single PT
To Interconnect
PT Clock
PT Preset
2
Fully Populated
AND Array
PT Reset
Shared PT Clock
Bus Input
From Tristate
Bus Track
Macrocell 3
PT 12
PT 13
PT 14
PT 15
From PTSA
PTSA Bypass
Single PT
To interconnect
PT Clock
PT Preset
3
PT Reset
Shared PT Clock
Bus Input
From Tristate
Bus Track
Macrocell 19
PT 76
PT 77
PT 78
PT 79
From PTSA
PTSA Bypass
Single PT
To Interconnect
PT Clock
PT Preset
19
PT Reset
Shared PT Clock
Bus Input
PT 80
PT 81
From Tristate Bus Track
To Output Control MUX
Note: Macrocells 9 and 10 do not support Tristate Bus Feedback.
Function Selector (E2 Cell Controlled)
5
LATTICE [ LATTICE SEMICONDUCTOR ]
