Specifications ispGDX80VA
Boundary Scan
The ispGDXVA devices provide IEEE1149.1a test capa- allows customers using boundary scan test to have full
bilityandISPprogrammingthroughastandardBoundary test capability with only a single BSDL file.
Scan Test Access Port (TAP) interface.
The ispGDXVA devices are identified by the 32-bit JTAG
The boundary scan circuitry on the ispGDXVA Family IDCODE register. The device ID assignments are listed
operates independently of the programmed pattern. This in Table 4.
Figure 10. Boundary Scan Register Circuit for I/O Pins
HIGHZ
EXTEST
SCANIN
(from previous
cell
TOE
BSCAN
Registers
BSCAN
Latches
Normal
Function
OE
0
1
D
D
D
Q
Q
Q
D
Q
EXTEST
PROG_MODE
Normal
Function
0
1
I/O Pin
D
Q
SCANOUT
(to next cell)
Shift DR
Clock DR
Update DR
Reset
Table 3. I/O Shift Register Order
DEVICE
I/O SHIFT REGISTER ORDER
ispGDX80VA
TDI, TOE, RESET, Y1, Y0, I/O B10 .. B19, I/O C0 .. C19, I/O D0 .. D9, I/O B9 .. B0, I/O A19.. A0,
I/O D19 .. D10, TDO
I/O Shift Reg Order/ispGDXVA
Table 4. ispGDX80VA Device ID Codes
DEVICE
32-BIT BOUNDARY SCAN ID CODE
ispGDX80VA
0001, 0000, 0011, 0101, 0000, 0000, 0100, 0011
ID Code/GDX80VA
21
LATTICE [ LATTICE SEMICONDUCTOR ]
