Specifications ispGDX80VA
Signal Descriptions
Signal Name
Description
I/O
Input/Output Pins – These are the general purpose bidirectional data pins. When used as outputs,
each may be independently latched, registered or tristated. They can also each assume one other
control function (OE, CLK/CLKEN, and MUXsel as described in the text).
RESET / I/O D10
This pin can be configured by the user through software to act as a RESET pin or as an I/O (I/O D10)
The default is RESET. If programmed to act as RESET, this pin is an active LOW Input Pin and resets
all I/O Register outputs when LOW.
Y1/CLKEN1/TOE, Input Pins – These can be either Global Clocks or Clock Enables. In addition, Y1 is multiplexed with
Y0/CLKEN0
TOE. Each pin can drive any or all I/O cell registers. The Test Output Enable (TOE) pin tristates all I/O
pins when LOW
EPEN
Input Pin – JTAG TAP Controller Enable Pin. When high, JTAG operation is enabled. When low,
JTAG TAP controller is driven to reset.
TDI
Input Pin – Serial data input during ISP programming or Boundary Scan mode.
Input Pin – Serial data clock during ISP programming or Boundary Scan mode.
Input Pin – Control input during ISP programming or Boundary Scan mode.
Output Pin – Serial data output during ISP programming or Boundary Scan mode.
Ground (GND)
TCK
TMS
TDO
GND
VCC
VCCIO
Vcc – Supply voltage (3.3V).
Input – This pin is used if optional 2.5V output is to be used. Every I/O can independently select either
3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin
must be connected to the VCC supply. Programmable pull-up resistors and bus-hold latches only draw
current from this supply.
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LATTICE [ LATTICE SEMICONDUCTOR ]
