Specifications ispGDX80VA
ispGDX Development System (Continued)
The GDF File
This example shows a simple, but complete, 32-bit 3:1
MUX design. Once completed, the compiler takes over.
The GDF file is a simple text description of the design
function, device and pin parameters. The file has four
parts: device selection, set and constant statements, a
pin section and a connection section. A sample file looks
like this:
Powerful Syntax
Lattice’sispGDXDesignSystemusessimple, butpower-
ful, syntax to easily define a design. The !(bang) operator
controls pin polarity and can be used in both the pin and
connection sections of the design definition. Dot exten-
sions define data inputs, select controls for the 4:1
multiplexor, and control inputs of sequential elements
andtri-statebuffers.Dotextensionsare.M#(MUXInput),
.S# (MUX Select), and control functions, such as .CLK,
.EN, .OE and .A (shown in adjacent table). Pin Attributes
// USE OPEN DRAIN are assigned in the pin section of the GDF as well.
// 32-Bit Data 3 to 1 Mux
DESIGN
datamux;
PART ispGDX160V-7Q208;
PARAM SECURITY ON;
PARAM OPENDRAIN ON;
// OPTION
// USE BUS HOLD
// LATCH OPTION
SLOWSLEW selects the slow slew rate for an output
buffer. The Pull parameter can be used to select the
internal pull-up or bus hold latch. OPEN drain can be
used to select open drain operation. The COMB attribute
distinguishesthestructureforbidirectionalpins. IfCOMB
is used, the input register, or latch, of an output buffer will
be applied to bidirectional pins.
PARAM PULL HOLD;
SET BUS_A
SET BUS_B
SET BUS_C
SET BUS_D
[dataA31..dataA0];
[dataB31..dataB0];
[dataC31..dataC0];
[dataD31..dataD0];
PleaseconsulttheispGDXDevelopmentSystemManual
for full details.
INPUT BUS_A
INPUT BUS_B
INPUT BUS_C
OUTPUT BUS_D
{A31..A0};
{B31..B0};
{C31..C0};
{D31..D0};
ispGDX GDF File Dot Extensions
Type
Dot Ext.
.M0
Description
MUXA Data input to 4:1 MUX
MUXB Data input to 4:1 MUX
MUXC Data Input to 4:1 MUX
MUXD Data input to 4:1 MUX
MUX0 Selection input to 4:1 MUX
MUX1 Selection input to 4:1 MUX
Clock for a register
.M1
MUX
Input
INPUT [oe] {B37};
INPUT [clk] {B36};
.M2
.M3
INPUT [sel1]
INPUT [sel0]
{B38};
{B39};
.S0
MUX
Selection
.S1
.CLK
.EN
BEGIN
Latch enable for a latch signal
BUS_D.m0 = BUS_A;
BUS_D.m1 = BUS_B;
BUS_D.m2 = BUS_C;
BUS_D.m3 = VCC;
Control
.OE
Output enable for 3-state output
or bidirectional signal
.CE
.A
Clock enable for register clock
// Default all
// outputs to VCC
MUX
Output
Adjacent MUX output of an I/O cell
ispGDXV Dot Ext
BUS_D.s1 = sel1;
BUS_D.s0 = sel0;
BUS_D.oe = oe;
BUS_D.clk = clk;
END
18
LATTICE [ LATTICE SEMICONDUCTOR ]
