Specifications ispLSI and pLSI 1032E
1
Internal Timing Parameters
-125
MIN. MAX. MIN. MAX.
-100
PARAM.
#
DESCRIPTION
UNITS
Outputs
1.3
9.9
4.3
4.3
2.7
2.0
10.0
5.1
–
–
–
–
–
–
–
–
–
–
49 Output Buffer Delay
ns
ns
ns
ns
ns
t
t
t
t
t
ob
50 Output Buffer Delay, Slew Limited Adder
51 I/O Cell OE to Output Enabled
52 I/O Cell OE to Output Disabled
53 Global OE
sl
oen
odis
goe
5.1
3.9
Clocks
1.4
1.4
1.8
0.0
1.8
1.5
1.5
1.8
0.0
1.8
1.4
1.4
0.8
0.0
0.8
1.5
1.5
0.8
0.0
0.8
54 Clk Delay, Y0 to Global GLB Clk Line (Ref. clk)
55 Clk Delay, Y1 or Y2 to Global GLB Clk Line
56 Clk Delay, Clock GLB to Global GLB Clk Line
57 Clk Delay, Y2 or Y3 to I/O Cell Global Clk Line
58 Clk Delay, Clk GLB to I/O Cell Global Clk Line
ns
ns
ns
ns
ns
t
t
t
t
t
gy0
gy1/2
gcp
ioy2/3
iocp
Global Reset
2.8
4.3
–
–
59 Global Reset to GLB and I/O Registers
ns
tgr
Table 2-0037A/1032E
1. Internal Timing Parameters are not tested and are for reference only.
9
LATTICE [ LATTICE SEMICONDUCTOR ]
