Specifications ispLSI and pLSI 1032E
External Timing Parameters
Over Recommended Operating Conditions
TEST 4
COND.
-125
-100
DESCRIPTION1
UNITS
2
PARAMETER
#
MIN. MAX. MIN. MAX.
A
A
A
–
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback 3
–
–
7.5
10.0
–
–
10.0
12.5
–
ns
ns
t
pd1
2
3
4
5
6
7
8
9
–
t
f
f
f
t
t
pd2
125
91.0
167
5.0
–
100
71.0
125
7.0
–
MHz
MHz
MHz
ns
max (Int.)
max (Ext.)
max (Tog.)
su1
1
Clock Frequency with External Feedback
(
)
–
–
tsu2 + tco1
1
–
Clock Frequency, Max. Toggle
(
)
–
–
twh + tw1
–
GLB Reg. Setup Time before Clock,4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
–
–
A
5.0
6.0
ns
co1
–
–
0.0
6.0
–
–
–
0.0
8.0
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
h1
su2
–
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
6.0
–
7.0
–
co2
–
0.0
–
0.0
–
h2
A
–
10.0
–
13.5
–
r1
5.0
–
6.5
–
rw1
B
C
B
C
–
14 Input to Output Enable
12.0
12.0
7.0
7.0
–
15.0
15.0
9.0
9.0
–
ptoeen
ptoedis
goeen
goedis
wh
15 Input to Output Disable
–
–
16 Global OE Output Enable
–
–
17 Global OE Output Disable
–
–
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
3.0
3.0
3.0
4.0
4.0
3.5
–
–
–
wl
–
20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3)
21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
–
–
su3
–
0.0
–
0.0
–
ns
th3
Table 2-0030A/1032E
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
5
LATTICE [ LATTICE SEMICONDUCTOR ]
