Specifications
ispLSI and pLSI 1032E
Internal Timing Parameters
1
PARAM. #
2
DESCRIPTION
-125
-100
MIN. MAX. MIN. MAX.
–
–
3.0
0.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.1
4.5
–
–
–
–
2.9
–
–
0.3
1.9
–
–
4.6
4.6
2.3
1.8
2.0
2.3
2.8
3.8
3.9
4.0
3.6
5.0
5.0
0.4
–
–
2.3
4.9
3.9
5.4
4.0
1.0
0.0
–
–
3.5
0.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.5
5.8
–
–
–
–
3.5
–
–
0.3
2.3
–
–
5.0
5.0
2.7
1.9
2.4
2.4
3.0
4.2
5.3
5.3
4.6
5.8
6.3
1.0
–
–
2.5
6.2
4.5
7.2
4.7
1.0
0.0
UNITS
Inputs
t
iobp
t
iolat
t
iosu
t
ioh
t
ioco
t
ior
t
din
GRP
22 I/O Register Bypass
23 I/O Latch Delay
24 I/O Register Setup Time before Clock
25 I/O Register Hold Time after Clock
26 I/O Register Clock to Out Delay
27 I/O Register Reset to Out Delay
28 Dedicated Input Delay
29 GRP Delay, 1 GLB Load
30 GRP Delay, 4 GLB Loads
31 GRP Delay, 8 GLB Loads
32 GRP Delay, 16 GLB Loads
33 GRP Delay, 32 GLB Loads
34 4 Prod.Term Bypass Path Delay (Combinatorial)
35 4 Prod. Term Bypass Path Delay (Registered)
36 1 Prod.Term/XOR Path Delay
37 20 Prod. Term/XOR Path Delay
38 XOR Adjacent Path Delay
3
39 GLB Register Bypass Delay
40 GLB Register Setup Time before Clock
41 GLB Register Hold Time after Clock
42 GLB Register Clock to Output Delay
43 GLB Register Reset to Output Delay
44 GLB Prod.Term Reset to Register Delay
45 GLB Prod. Term Output Enable to I/O Cell Delay
46 GLB Prod. Term Clock Delay
47 ORP Delay
48 ORP Bypass Delay
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
grp1
t
grp4
t
grp8
t
grp16
t
grp32
GLB
t
4ptbpc
t
4ptbpr
t
1ptxor
t
20ptxor
t
xoradj
t
gbp
t
gsu
t
gh
t
gco
t
gro
t
ptre
t
ptoe
t
ptck
ORP
t
orp
t
orpbp
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/1032E
7
LATTICE [ LATTICE SEMICONDUCTOR ]
