Specifications ispLSI and pLSI 1032E
1
Internal Timing Parameters
-80
-70
-90
PARAM.
#
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
Outputs
1.7
10.0
5.3
2.1
10.0
5.7
–
–
–
–
–
2.6
10.0
6.2
49 Output Buffer Delay
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
t
t
t
t
t
ob
50 Output Buffer Delay, Slew Limited Adder
51 I/O Cell OE to Output Enabled
52 I/O Cell OE to Output Disabled
53 Global OE
sl
oen
odis
goe
5.3
5.7
6.2
3.7
4.3
5.8
Clocks
1.4
2.9
1.8
0.0
1.8
1.5
3.1
1.8
0.0
1.8
1.5 1.5
1.5 1.5
0.8 1.8
0.0 0.0
0.8 1.8
54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
55 Clock Delay, Y1 or Y2 to Global GLB Clock Line
56 Clock Delay, Clock GLB to Global GLB Clock Line
57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
58 Clock Delay, Clock GLB to I/O Cell Global Clock Line
1.4
2.4
0.8
0.0
0.8
1.5
2.6
0.8
0.0
0.8
ns
ns
ns
ns
ns
t
t
t
t
t
gy0
gy1/2
gcp
ioy2/3
iocp
Global Reset
4.5
4.5
–
4.6
59 Global Reset to GLB and I/O Registers
–
–
ns
tgr
Table 2-0037B/1032E
1. Internal Timing Parameters are not tested and are for reference only.
10
LATTICE [ LATTICE SEMICONDUCTOR ]
