Specifications ispLSI and pLSI 1032E
1
Internal Timing Parameters
-80
-70
-90
2
PARAM.
#
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
Inputs
–
–
22 I/O Register Bypass
23 I/O Latch Delay
–
–
ns
ns
ns
ns
ns
ns
ns
0.3
2.3
–
t
t
t
t
t
t
t
iobp
iolat
iosu
ioh
0.3
2.7
–
–
–
0.3
3.3
–
3.5
0.0
–
24 I/O Register Setup Time before Clock
25 I/O Register Hold Time after Clock
26 I/O Register Clock to Out Delay
27 I/O Register Reset to Out Delay
28 Dedicated Input Delay
3.5
0.0
–
4.0
0.0
–
–
–
–
5.0
5.0
2.6
ioco
ior
5.4
5.4
2.8
6.1
6.0
2.8
–
–
–
–
–
din
–
GRP
–
–
–
–
–
29 GRP Delay, 1 GLB Load
30 GRP Delay, 4 GLB Loads
31 GRP Delay, 8 GLB Loads
32 GRP Delay, 16 GLB Loads
33 GRP Delay, 32 GLB Loads
–
–
–
–
–
ns
ns
ns
ns
ns
2.1
2.3
2.6
3.2
4.4
t
t
t
grp1
grp4
grp8
2.2
2.5
2.8
3.5
4.8
–
–
–
–
–
2.5
2.5
3.2
4.0
5.6
t
grp16
t
grp32
GLB
–
–
34 4 Prod.Term Bypass Path Delay (Combinatorial)
35 4 Prod. Term Bypass Path Delay (Registered)
36 1 Prod.Term/XOR Path Delay
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.7
6.1
5.6
6.8
7.1
0.4
–
t
4ptbpc
4ptbpr
1ptxor
20ptxor
xoradj
gbp
7.1
6.7
6.6
7.8
8.2
1.3
–
–
–
8.8
7.2
8.3
8.7
9.2
1.6
–
t
t
t
t
t
t
t
t
t
t
t
t
–
–
–
–
37 20 Prod. Term/XOR Path Delay
38 XOR Adjacent Path Delay 3
–
–
–
–
–
–
–
39 GLB Register Bypass Delay
–
0.2
6.8
–
40 GLB Register Setup Time before Clock
41 GLB Register Hold Time after Clock
42 GLB Register Clock to Output Delay
43 GLB Register Reset to Output Delay
44 GLB Prod.Term Reset to Register Delay
45 GLB Prod. Term Output Enable to I/O Cell Delay
46 GLB Prod. Term Clock Delay
0.5
7.9
–
gsu
0.5
8.8
–
–
gh
–
–
2.9
6.3
5.1
7.1
5.3
gco
2.9
6.4
5.5
8.0
2.9
6.8
5.8
9.0
6.2
–
–
gro
–
–
–
ptre
–
–
–
ptoe
ptck
–
4.1
4.5
5.8 4.8
ORP
–
–
47 ORP Delay
–
–
ns
ns
1.0
0.0
t
t
orp
1.0
0.0
–
–
1.0
0.0
48 ORP Bypass Delay
orpbp
Table 2-0036B/1032E
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
8
LATTICE [ LATTICE SEMICONDUCTOR ]
