Specifications ispLSI and pLSI 1032
1
Internal Timing Parameters
-90
-80
-60
2
PARAMETER
DESCRIPTION
UNITS
#
MIN. MAX. MIN. MAX.
MIN. MAX.
Inputs
–
–
1.6
2.4
–
–
–
2.0
3.0
–
2.7
4.0
–
t
t
t
t
t
t
t
iobp
iolat
iosu
ioh
I/O Register Bypass
–
–
20
21
22
23
24
25
26
ns
ns
ns
ns
ns
ns
ns
I/O Latch Delay
4.8
2.1
–
5.5
1.0
–
I/O Register Setup Time before Clock
I/O Register Hold Time after Clock
I/O Register Clock to Out Delay
I/O Register Reset to Out Delay
Dedicated Input Delay
7.3
1.3
–
–
–
–
2.4
2.8
3.2
3.0
2.5
4.0
ioco
ior
4.0
3.3
5.3
–
–
–
–
–
din
–
GRP
–
–
–
–
–
–
1.2
1.6
2.4
3.0
3.6
6.4
–
–
–
–
–
–
1.5
2.0
3.0
3.8
4.5
8.0
2.0
2.7
4.0
5.0
6.0
10.6
t
t
t
t
t
t
grp1
GRP Delay, 1 GLB Load
GRP Delay, 4 GLB Loads
GRP Delay, 8 GLB Loads
GRP Delay, 12 GLB Loads
GRP Delay, 16 GLB Loads
GRP Delay, 32 GLB Loads
–
–
–
–
–
–
27
28
29
30
31
32
ns
ns
ns
ns
ns
ns
grp4
grp8
grp12
grp16
grp32
GLB
–
–
5.2
5.7
7.0
8.2
0.8
–
–
–
6.5
7.0
8.0
9.5
1.0
–
4 Product Term Bypass Path Delay
1 Product Term/XOR Path Delay
20 Product Term/XOR Path Delay
t
t
t
t
t
t
t
t
t
t
t
t
4ptbp
1ptxor
20ptxor
xoradj
gbp
33
34
35
36
37
38
39
40
41
42
43
44
–
–
8.6
9.3
10.6
12.7
1.3
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
3
–
–
XOR Adjacent Path Delay
–
–
–
GLB Register Bypass Delay
–
1.2
3.6
–
1.0
4.5
–
gsu
GLB Register Setup Time before Clock
GLB Register Hold Time after Clock
GLB Register Clock to Output Delay
GLB Register Reset to Output Delay
GLB Product Term Reset to Register Delay
GLB Product Term Output Enable to I/O Cell Delay
GLB Product Term Clock Delay
1.3
6.0
–
–
–
gh
–
1.6
2.0
8.0
7.8
2.0
2.5
10.0
9.0
gco
2.7
3.3
13.3
12.0
–
–
gr
–
–
–
ptre
–
–
–
ptoe
ptck
–
2.8 6.0 3.5 7.5
4.6 9.9
ORP
–
–
2.4
0.4
–
–
2.5
0.5
3.3
0.7
t
orp
ORP Delay
–
–
45
46
ns
ns
ORP Bypass Delay
torpbp
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
6
1996 ISP Encyclopedia
LATTICE [ LATTICE SEMICONDUCTOR ]
