Specifications ispLSI and pLSI 1032
Functional Block Diagram
Figure 1. ispLSI and pLSI 1032 Functional Block Diagram
I/O I/O I/OI/O
63 62 61 60
I/O I/OI/OI/O
59 58 57 56
I/O I/O I/O I/O
55 54 53 52
I/O I/O I/O I/O
51 50 49 48
IN IN
7
6
RESET
Input Bus
Output Routing Pool (ORP)
Generic
Logic Blocks
(GLBs)
IN 5
IN 4
D7
D6
D5
D4
D3
D2
D1
D0
I/O 47
I/O 46
I/O 45
I/O 44
C7
C6
C5
C4
I/O 0
I/O 1
I/O 2
I/O 3
A0
A1
A2
A3
I/O 43
I/O 42
I/O 41
I/O 4
I/O 5
I/O 6
I/O 7
I/O 40
Global
Routing
Pool
I/O 39
I/O 38
I/O 37
I/O 36
C3
C2
C1
C0
(GRP)
I/O 8
A4
A5
A6
A7
I/O 9
I/O 10
I/O 11
I/O 35
I/O 34
I/O 33
I/O 32
I/O 12
I/O 13
I/O 14
I/O 15
*SDI/IN 0
CLK 0
B0
B1
B2
B3
B4
B5
B6
B7
*MODE/IN 1
CLK 1
CLK 2
Clock
Distribution
Network
IOCLK 0
IOCLK 1
Output Routing Pool (ORP)
Input Bus
Megablock
*ispEN/NC
I/O I/O I/O I/O
16 17 18 19
I/O I/O I/O I/O
20 21 22 23
I/O I/O I/O I/O
24 25 26 27
I/O I/O I/O I/O
28 29 30 31
Y
0
Y
1
Y
2
Y
3
*SDO/IN 2
*SCLK/IN 3
0139(1)-32-isp
*ISP Control Functions for ispLSI 1032 Only
The devices also have 64 I/O cells, each of which is TheGRPhasasitsinputstheoutputsfromalloftheGLBs
directly connected to an I/O pin. Each I/O cell can be and all of the inputs from the bi-directional I/O cells. All of
individually programmed to be a combinatorial input, these signals are made available to the inputs of the
registered input, latched input, output or bi-directional GLBs. Delays through the GRP have been equalized to
I/O pin with 3-state control. Additionally, all outputs are minimize timing skew.
polarity selectable, active high or active low. The signal
Clocks in the ispLSI and pLSI 1032 devices are selected
levelsareTTLcompatiblevoltagesandtheoutputdrivers
using the Clock Distribution Network. Four dedicated
can source 4 mA or sink 8 mA.
clock pins (Y0, Y1, Y2 and Y3) are brought into the
Eight GLBs, 16 I/O cells, two dedicated inputs and one distribution network, and five clock outputs (CLK 0, CLK
ORP are connected together to make a Megablock (see 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route
figure 1). The outputs of the eight GLBs are connected to clocks to the GLBs and I/O cells. The Clock Distribution
a set of 16 universal I/O cells by the ORP. The I/O cells Network can also be driven from a special clock GLB (C0
within the Megablock also share a common Output on the ispLSI and pLSI 1032 devices). The logic of this
Enable (OE) signal. The ispLSI and pLSI 1032 devices GLB allows the user to create an internal clock from a
contain four of these Megablocks.
combination of internal signals within the device.
2
1996 ISP Encyclopedia
LATTICE [ LATTICE SEMICONDUCTOR ]
