Specifications ispLSI and pLSI 1032
1
Internal Timing Parameters
-90
-80
-60
2
PARAMETER
DESCRIPTION
UNITS
#
MIN. MAX.
MIN. MAX. MIN. MAX.
Outputs
–
–
–
2.4
4.0
4.0
t
t
t
ob
Output Buffer Delay
–
–
–
3.0
5.0
5.0
–
–
–
4.0
6.7
6.7
47
48
49
ns
ns
ns
I/O Cell OE to Output Enabled
I/O Cell OE to Output Disabled
oen
odis
Clocks
3.6 3.6
2.8 4.4
0.8 4.0
2.8 4.4
0.8 4.0
t
t
t
t
t
gy0
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
Clock Delay, Y1 or Y2 to Global GLB Clock Line
Clock Delay, Clock GLB to Global GLB Clock Line
Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
Clock Delay, Clock GLB to I/O Cell Global Clock Line
4.5 4.5 6.0 6.0
3.5 5.5 4.6 7.3
1.0 5.0 1.3 6.6
3.5 5.5 4.6 7.3
1.0 5.0 1.3 6.6
50
51
52
53
54
ns
ns
ns
ns
ns
gy1/2
gcp
ioy2/3
iocp
Global Reset
–
8.2
tgr
Global Reset to GLB and I/O Registers
–
9.0
–
12.0
55
ns
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
7
1996 ISP Encyclopedia
LATTICE [ LATTICE SEMICONDUCTOR ]
