IS42S16400F
IC42S16400F
3. Current state definitions:
ꢀ
ꢀ
Idle:ꢀTheꢀbankꢀhasꢀbeenꢀprecharged,ꢀandꢀtr p has been met.
RowꢀActive:ꢀAꢀrowꢀinꢀtheꢀbankꢀhasꢀbeenꢀactivated,ꢀandꢀtr c D has been met. No data bursts/accesses and no register
accesses are in progress.
ꢀ
ꢀ
Read:ꢀAꢀREADꢀburstꢀhasꢀbeenꢀinitiated,ꢀwithꢀautoꢀprechargeꢀdisabled,ꢀandꢀhasꢀnotꢀyetꢀterminatedꢀorꢀbeenꢀtermi-
nated.
Write:ꢀAꢀWRITEꢀburstꢀhasꢀbeenꢀinitiated,ꢀwithꢀautoꢀprechargeꢀdisabled,ꢀandꢀhasꢀnotꢀyetꢀterminatedꢀorꢀbeenꢀtermi-
nated.
ꢀ 4.ꢀTheꢀfollowingꢀstatesꢀmustꢀnotꢀbeꢀinterruptedꢀbyꢀaꢀcommandꢀissuedꢀtoꢀtheꢀsameꢀbank.ꢀCOMMANDꢀINHIBITꢀorꢀNOPꢀcommands,ꢀ
or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable com-
mandsꢀtoꢀtheꢀotherꢀbankꢀareꢀdeterminedꢀbyꢀitsꢀcurrentꢀstateꢀandꢀCURRENTꢀSTATEꢀBANKꢀnꢀtruthꢀtables.
ꢀ
ꢀ
ꢀ
Precharging:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀPRECHARGEꢀcommandꢀandꢀendsꢀwhenꢀtr p ꢀisꢀmet.ꢀOnceꢀtr p is met, the bank
will be in the idle state.
RowꢀActivating:ꢀStartsꢀwithꢀregistrationꢀofꢀanꢀACTIVEꢀcommandꢀandꢀendsꢀwhenꢀtr c D ꢀisꢀmet.ꢀOnceꢀtr c D is met, the bank will
be in the row active state.
Readꢀw/Auto
PrechargeꢀEnabled:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀREADꢀcommandꢀwithꢀautoꢀprechargeꢀenabledꢀandꢀendsꢀwhenꢀtr p has been
met.ꢀOnceꢀtr p is met, the bank will be in the idle state.
Write w/Auto
PrechargeꢀEnabled:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀWRITEꢀcommandꢀwithꢀautoꢀprechargeꢀenabledꢀandꢀendsꢀwhenꢀtr p has been
met.ꢀOnceꢀtr p is met, the bank will be in the idle state.
ꢀ 5.ꢀTheꢀfollowingꢀstatesꢀmustꢀnotꢀbeꢀinterruptedꢀbyꢀanyꢀexecutableꢀcommand;ꢀCOMMANDꢀINHIBITꢀorꢀNOPꢀcommandsꢀmustꢀbeꢀ
applied on each positive clock edge during these states.
ꢀ
Refreshing:ꢀStartsꢀwithꢀregistrationꢀofꢀanꢀAUTOꢀREFRESHꢀcommandꢀandꢀendsꢀwhenꢀtr c ꢀisꢀmet.ꢀOnceꢀtr c is met, the
SDRAMꢀwillꢀbeꢀinꢀtheꢀallꢀbanksꢀidleꢀstate.
Accessing Mode
ꢀ
Register:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀLOADꢀMODEꢀREGISTERꢀcommandꢀandꢀendsꢀwhenꢀtm r D ꢀhasꢀbeenꢀmet.ꢀOnceꢀ
tm r D ꢀisꢀmet,ꢀtheꢀSDRAMꢀwillꢀbeꢀinꢀtheꢀallꢀbanksꢀidleꢀstate.
PrechargingꢀAll:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀPRECHARGEꢀALLꢀcommandꢀandꢀendsꢀwhenꢀtr p ꢀisꢀmet.ꢀOnceꢀtr p is met, all
banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
ꢀ 7.ꢀNotꢀbank-specific;ꢀrequiresꢀthatꢀallꢀbanksꢀareꢀidle.
ꢀ 8.ꢀMayꢀorꢀmayꢀnotꢀbeꢀbank-specific;ꢀifꢀallꢀbanksꢀareꢀtoꢀbeꢀprecharged,ꢀallꢀmustꢀbeꢀinꢀaꢀvalidꢀstateꢀforꢀprecharging.
ꢀ 9.ꢀNotꢀbank-specific;ꢀBURSTꢀTERMINATEꢀaffectsꢀtheꢀmostꢀrecentꢀREADꢀorꢀWRITEꢀburst,ꢀregardlessꢀofꢀbank.
ꢀ10.ꢀREADsꢀorꢀWRITEsꢀlistedꢀinꢀtheꢀCommandꢀ(Action)ꢀcolumnꢀincludeꢀREADsꢀorꢀWRITEsꢀwithꢀautoꢀprechargeꢀenabledꢀandꢀ
READsꢀorꢀWRITEsꢀwithꢀautoꢀprechargeꢀdisabled.
ꢀ11.ꢀDoesꢀnotꢀaffectꢀtheꢀstateꢀofꢀtheꢀbankꢀandꢀactsꢀasꢀaꢀNOPꢀtoꢀthatꢀbank.
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
03/19/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
