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IC42S16400F-6TL 参数 Datasheet PDF下载

IC42S16400F-6TL图片预览
型号: IC42S16400F-6TL
PDF下载: 下载PDF文件 查看货源
内容描述: 1梅格位×16位× 4银行( 64兆位)同步动态RAM [1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM]
分类和应用: 存储内存集成电路光电二极管动态存储器时钟
文件页数/大小: 55 页 / 822 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IS42S16400F  
IC42S16400F  
FUNCTION (InꢀDetail)  
READ  
A0-A11ꢀareꢀaddressꢀinputsꢀsampledꢀduringꢀtheꢀACTIVEꢀ  
(row-address A0-A11)ꢀandꢀREAD/WRITEꢀcommandꢀ(A0-A7ꢀ  
withA10definingautoPRECHARGE). A10 is sampled during  
aꢀPRECHARGEꢀcommandꢀtoꢀdetermineꢀifꢀallꢀbanksꢀareꢀtoꢀ  
beꢀPRECHARGEDꢀ(A10 HIGH)ꢀorꢀbankꢀselectedꢀbyꢀBA0,ꢀ  
BA1ꢀ(LOW).ꢀꢀTheꢀaddressꢀinputsꢀalsoꢀprovideꢀtheꢀop-codeꢀ  
duringꢀaꢀLOADꢀMODEꢀREGISTERꢀcommand.  
TheREADcommandselectsthebankfromBA0,BA1inputsꢀ  
and starts a burst read access to an active row. Inputs  
A0-A7ꢀprovidesꢀtheꢀstartingꢀcolumnꢀlocation.ꢀWhenꢀA10ꢀisꢀ  
HIGH,thiscommandfunctionsasanAUTOPRECHARGEꢀ  
command. When the auto precharge is selected, the row  
beingaccessedwillbeprechargedattheendoftheREADꢀ  
burst.ꢀTheꢀrowꢀwillꢀremainꢀopenꢀforꢀsubsequentꢀaccessesꢀ  
whenAUTOPRECHARGEisnotselected.DQ’sreadꢀ  
dataꢀisꢀsubjectꢀtoꢀtheꢀlogicꢀlevelꢀonꢀtheꢀDQMꢀinputsꢀtwoꢀ  
clocksꢀearlier.ꢀWhenꢀaꢀgivenꢀDQMꢀsignalꢀwasꢀregisteredꢀ  
HIGH,ꢀtheꢀcorrespondingꢀDQ’sꢀwillꢀbeꢀHigh-Zꢀtwoꢀclocksꢀ  
later.DQ’sꢀwillꢀprovideꢀvalidꢀdataꢀwhenꢀtheꢀDQMꢀsignalꢀ  
wasꢀregisteredꢀLOW.  
BankꢀSelectꢀAddressꢀ(BA0ꢀandꢀBA1) defines which bank  
theꢀACTIVE,ꢀREAD,ꢀWRITEꢀorꢀPRECHARGEꢀcommandꢀ  
is being applied.  
CAS,inconjunctionwiththeRASandWE,formsthedevice  
command.ꢀSeeꢀtheꢀ“CommandꢀTruthꢀTable”ꢀforꢀdetailsꢀonꢀ  
device commands.  
WRITE  
TheꢀCKEꢀinputꢀdeterminesꢀwhetherꢀtheꢀCLKꢀinputꢀisꢀen-  
abled.ꢀTheꢀnextꢀrisingꢀedgeꢀofꢀtheꢀCLKꢀsignalꢀwillꢀbeꢀvalidꢀ  
whenꢀisꢀCKEꢀHIGHꢀandꢀinvalidꢀwhenꢀLOW.ꢀWhenꢀCKEꢀisꢀ  
LOW,thedevicewillbeineitherpower-downmode,CLOCKꢀ  
SUSPENDꢀmode,ꢀorꢀSELF-REFRESHꢀmode.ꢀCKEꢀisꢀanꢀ  
asynchronous input.  
A burst write access to an active row is initiated with the  
WRITEcommand.BA0,BA1inputsselectsthebank,ꢀ  
and the starting column location is provided by inputs  
A0-A7.WhetherornotAUTO-PRECHARGEisusedisꢀ  
determined by A10.  
CLKꢀisꢀtheꢀmasterꢀclockꢀinputꢀforꢀthisꢀdevice.ꢀExceptꢀforꢀ  
CKE,ꢀallꢀinputsꢀtoꢀthisꢀdeviceꢀareꢀacquiredꢀinꢀsynchroniza-  
tion with the rising edge of this pin.  
Theꢀrowꢀbeingꢀaccessedꢀwillꢀbeꢀprechargedꢀatꢀtheꢀendꢀofꢀ  
theꢀWRITEburst,ifAUTOPRECHARGEisselected.Ifꢀ  
AUTOꢀPRECHARGEꢀisꢀnotꢀselected,ꢀtheꢀrowꢀwillꢀremainꢀ  
open for subsequent accesses.  
TheꢀCS input determines whether command input is en-  
abled within the device. Command input is enabled when  
CS isLOW,anddisabledwithCS isHIGH.ꢀThedeviceꢀ  
remains in the previous state when CS isꢀHIGH.ꢀDQ0ꢀtoꢀ  
DQ15areDQpins.DQthroughthesepinscanbecontrolledꢀ  
inꢀbyteꢀunitsꢀusingꢀtheꢀLDQMꢀandꢀUDQMꢀpins.  
A memory array is written with corresponding input data  
onꢀDQ’sꢀandꢀDQMꢀinputꢀlogicꢀlevelꢀappearingꢀatꢀtheꢀsameꢀ  
time.ꢀꢀDataꢀwillꢀbeꢀwrittenꢀtoꢀmemoryꢀwhenꢀDQMꢀsignalꢀisꢀ  
LOW.ꢀꢀWhenꢀDQMꢀisꢀHIGH,ꢀtheꢀcorrespondingꢀdataꢀinputsꢀ  
willꢀbeꢀignored,ꢀandꢀaꢀWRITEꢀwillꢀnotꢀbeꢀexecutedꢀtoꢀthatꢀ  
byte/column location.  
LDQMꢀandꢀUDQMꢀcontrolꢀtheꢀlowerꢀandꢀupperꢀbytesꢀofꢀ  
theꢀDQꢀbuffers.ꢀInꢀreadꢀmode,ꢀLDQMꢀandꢀUDQMꢀcontrolꢀ  
theꢀ outputꢀ buffer.Whenꢀ LDQMꢀ orꢀ UDQMꢀ isꢀ LOW,ꢀ theꢀ  
corresponding buffer byte is enabled, and when HIGH,  
disabled.ꢀTheꢀoutputsꢀgoꢀtoꢀtheꢀHIGHꢀImpedanceꢀStateꢀ  
whenꢀLDQM/UDQMꢀisꢀHIGH.ꢀThisꢀfunctionꢀcorrespondsꢀ  
to OE inꢀconventionalꢀDRAMs.ꢀInꢀwriteꢀmode,ꢀLDQMꢀandꢀ  
UDQMꢀcontrolꢀtheꢀinputꢀbuffer.ꢀWhenꢀLDQMꢀorꢀUDQMꢀisꢀ  
LOW,ꢀtheꢀcorrespondingꢀbufferꢀbyteꢀisꢀenabled,ꢀandꢀdataꢀ  
canbewrittentothedevice.ꢀWhenLDQMorUDQMisꢀ  
HIGH, input data is masked and cannot be written to the  
device.  
PRECHARGE  
ThePRECHARGEcommandisusedtodeactivatetheꢀ  
open row in a particular bank or the open row in all banks.  
BA0,ꢀBA1ꢀcanꢀbeꢀusedꢀtoꢀselectꢀwhichꢀbankꢀisꢀprechargedꢀ  
orꢀ theyꢀ areꢀ treatedꢀ asꢀ “Don’tꢀ Care”.ꢀ ꢀ A10ꢀ determinedꢀ  
whetheroneorallbanksareprecharged.Afterexecut-  
ingꢀ thisꢀ command,ꢀ theꢀ nextꢀ commandꢀ forꢀ theꢀ selectedꢀ  
banks(s)ꢀisꢀexecutedꢀafterꢀpassageꢀofꢀtheꢀperiodꢀtRP, which  
isꢀtheꢀperiodꢀrequiredꢀforꢀbankꢀprecharging.ꢀꢀꢀOnceꢀaꢀbankꢀ  
has been precharged, it is in the idle state and must be  
activatedꢀpriorꢀtoꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀbeingꢀ  
issued to that bank.  
RAS, in conjunction with CAS and WE , forms the device  
command.ꢀSeeꢀtheCommandTruthTable”ꢀitemꢀforꢀdetailsꢀ  
on device commands.  
AUTO PRECHARGE  
WE , in conjunction with RAS and CAS , forms the device  
command.ꢀSeeꢀtheCommandTruthTable”ꢀitemꢀforꢀdetailsꢀ  
on device commands.  
TheꢀAUTOꢀPRECHARGEꢀfunctionꢀensuresꢀthatꢀtheꢀpre-  
charge is initiated at the earliest valid stage within a burst.  
Thisꢀfunctionꢀallowsꢀforꢀindividual-bankꢀprechargeꢀwithoutꢀ  
requiringꢀanꢀexplicitꢀcommand.ꢀꢀA10ꢀtoꢀenablesꢀtheꢀAUTOꢀ  
PRECHARGEfunctioninconjunctionwithaspecificREADꢀ  
orWRITEcommand.ꢀForꢀeachꢀindividualꢀREADꢀorWRITEꢀ  
command, auto precharge is either enabled or disabled.  
VDDq is the output buffer power supply.  
VDD is the device internal power supply.  
GNDq is the output buffer ground.  
GNDꢀisꢀtheꢀdeviceꢀinternalꢀground.  
4
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. A  
03/19/08