IS42S16400F
IC42S16400F
FUNCTION (InꢀDetail)
READ
A0-A11ꢀareꢀaddressꢀinputsꢀsampledꢀduringꢀtheꢀACTIVEꢀ
(row-address A0-A11)ꢀandꢀREAD/WRITEꢀcommandꢀ(A0-A7ꢀ
withꢀA10ꢀdefiningꢀautoꢀPRECHARGE). A10 is sampled during
aꢀPRECHARGEꢀcommandꢀtoꢀdetermineꢀifꢀallꢀbanksꢀareꢀtoꢀ
beꢀPRECHARGEDꢀ(A10 HIGH)ꢀorꢀbankꢀselectedꢀbyꢀBA0,ꢀ
BA1ꢀ(LOW).ꢀꢀTheꢀaddressꢀinputsꢀalsoꢀprovideꢀtheꢀop-codeꢀ
duringꢀaꢀLOADꢀMODEꢀREGISTERꢀcommand.
TheꢀREADꢀcommandꢀselectsꢀtheꢀbankꢀfromꢀBA0,ꢀBA1ꢀinputsꢀ
and starts a burst read access to an active row. Inputs
A0-A7ꢀprovidesꢀtheꢀstartingꢀcolumnꢀlocation.ꢀꢀWhenꢀA10ꢀisꢀ
HIGH,ꢀthisꢀcommandꢀfunctionsꢀasꢀanꢀAUTOꢀPRECHARGEꢀ
command. When the auto precharge is selected, the row
beingꢀaccessedꢀwillꢀbeꢀprechargedꢀatꢀtheꢀendꢀofꢀtheꢀREADꢀ
burst.ꢀTheꢀrowꢀwillꢀremainꢀopenꢀforꢀsubsequentꢀaccessesꢀ
whenꢀAUTOꢀPRECHARGEꢀisꢀnotꢀselected.ꢀꢀDQ’sꢀreadꢀ
dataꢀisꢀsubjectꢀtoꢀtheꢀlogicꢀlevelꢀonꢀtheꢀDQMꢀinputsꢀtwoꢀ
clocksꢀearlier.ꢀWhenꢀaꢀgivenꢀDQMꢀsignalꢀwasꢀregisteredꢀ
HIGH,ꢀtheꢀcorrespondingꢀDQ’sꢀwillꢀbeꢀHigh-Zꢀtwoꢀclocksꢀ
later.ꢀDQ’sꢀwillꢀprovideꢀvalidꢀdataꢀwhenꢀtheꢀDQMꢀsignalꢀ
wasꢀregisteredꢀLOW.
BankꢀSelectꢀAddressꢀ(BA0ꢀandꢀBA1) defines which bank
theꢀACTIVE,ꢀREAD,ꢀWRITEꢀorꢀPRECHARGEꢀcommandꢀ
is being applied.
CAS,inconjunctionwiththeRASandWE,formsthedevice
command.ꢀSeeꢀtheꢀ“CommandꢀTruthꢀTable”ꢀforꢀdetailsꢀonꢀ
device commands.
WRITE
TheꢀCKEꢀinputꢀdeterminesꢀwhetherꢀtheꢀCLKꢀinputꢀisꢀen-
abled.ꢀTheꢀnextꢀrisingꢀedgeꢀofꢀtheꢀCLKꢀsignalꢀwillꢀbeꢀvalidꢀ
whenꢀisꢀCKEꢀHIGHꢀandꢀinvalidꢀwhenꢀLOW.ꢀWhenꢀCKEꢀisꢀ
LOW,ꢀtheꢀdeviceꢀwillꢀbeꢀinꢀeitherꢀpower-downꢀmode,ꢀCLOCKꢀ
SUSPENDꢀmode,ꢀorꢀSELF-REFRESHꢀmode.ꢀCKEꢀisꢀanꢀ
asynchronous input.
A burst write access to an active row is initiated with the
WRITEꢀcommand.ꢀꢀBA0,ꢀBA1ꢀinputsꢀselectsꢀtheꢀbank,ꢀ
and the starting column location is provided by inputs
A0-A7.ꢀWhetherꢀorꢀnotꢀAUTO-PRECHARGEꢀisꢀusedꢀisꢀ
determined by A10.
CLKꢀisꢀtheꢀmasterꢀclockꢀinputꢀforꢀthisꢀdevice.ꢀExceptꢀforꢀ
CKE,ꢀallꢀinputsꢀtoꢀthisꢀdeviceꢀareꢀacquiredꢀinꢀsynchroniza-
tion with the rising edge of this pin.
Theꢀrowꢀbeingꢀaccessedꢀwillꢀbeꢀprechargedꢀatꢀtheꢀendꢀofꢀ
theꢀWRITEꢀburst,ꢀifꢀAUTOꢀPRECHARGEꢀisꢀselected.ꢀIfꢀ
AUTOꢀPRECHARGEꢀisꢀnotꢀselected,ꢀtheꢀrowꢀwillꢀremainꢀ
open for subsequent accesses.
TheꢀCS input determines whether command input is en-
abled within the device. Command input is enabled when
CS isꢀLOW,ꢀandꢀdisabledꢀwithꢀCS isꢀHIGH.ꢀTheꢀdeviceꢀ
remains in the previous state when CS isꢀHIGH.ꢀDQ0ꢀtoꢀ
DQ15ꢀareꢀDQꢀpins.ꢀDQꢀthroughꢀtheseꢀpinsꢀcanꢀbeꢀcontrolledꢀ
inꢀbyteꢀunitsꢀusingꢀtheꢀLDQMꢀandꢀUDQMꢀpins.
A memory array is written with corresponding input data
onꢀDQ’sꢀandꢀDQMꢀinputꢀlogicꢀlevelꢀappearingꢀatꢀtheꢀsameꢀ
time.ꢀꢀDataꢀwillꢀbeꢀwrittenꢀtoꢀmemoryꢀwhenꢀDQMꢀsignalꢀisꢀ
LOW.ꢀꢀWhenꢀDQMꢀisꢀHIGH,ꢀtheꢀcorrespondingꢀdataꢀinputsꢀ
willꢀbeꢀignored,ꢀandꢀaꢀWRITEꢀwillꢀnotꢀbeꢀexecutedꢀtoꢀthatꢀ
byte/column location.
LDQMꢀandꢀUDQMꢀcontrolꢀtheꢀlowerꢀandꢀupperꢀbytesꢀofꢀ
theꢀDQꢀbuffers.ꢀInꢀreadꢀmode,ꢀLDQMꢀandꢀUDQMꢀcontrolꢀ
theꢀ outputꢀ buffer.ꢀWhenꢀ LDQMꢀ orꢀ UDQMꢀ isꢀ LOW,ꢀ theꢀ
corresponding buffer byte is enabled, and when HIGH,
disabled.ꢀTheꢀoutputsꢀgoꢀtoꢀtheꢀHIGHꢀImpedanceꢀStateꢀ
whenꢀLDQM/UDQMꢀisꢀHIGH.ꢀThisꢀfunctionꢀcorrespondsꢀ
to OE inꢀconventionalꢀDRAMs.ꢀInꢀwriteꢀmode,ꢀLDQMꢀandꢀ
UDQMꢀcontrolꢀtheꢀinputꢀbuffer.ꢀWhenꢀLDQMꢀorꢀUDQMꢀisꢀ
LOW,ꢀtheꢀcorrespondingꢀbufferꢀbyteꢀisꢀenabled,ꢀandꢀdataꢀ
canꢀbeꢀwrittenꢀtoꢀtheꢀdevice.ꢀWhenꢀLDQMꢀorꢀUDQMꢀisꢀ
HIGH, input data is masked and cannot be written to the
device.
PRECHARGE
TheꢀPRECHARGEꢀcommandꢀisꢀusedꢀtoꢀdeactivateꢀtheꢀ
open row in a particular bank or the open row in all banks.
BA0,ꢀBA1ꢀcanꢀbeꢀusedꢀtoꢀselectꢀwhichꢀbankꢀisꢀprechargedꢀ
orꢀ theyꢀ areꢀ treatedꢀ asꢀ “Don’tꢀ Care”.ꢀ ꢀ A10ꢀ determinedꢀ
whetherꢀoneꢀorꢀallꢀbanksꢀareꢀprecharged.ꢀAfterꢀexecut-
ingꢀ thisꢀ command,ꢀ theꢀ nextꢀ commandꢀ forꢀ theꢀ selectedꢀ
banks(s)ꢀisꢀexecutedꢀafterꢀpassageꢀofꢀtheꢀperiodꢀtRP, which
isꢀtheꢀperiodꢀrequiredꢀforꢀbankꢀprecharging.ꢀꢀꢀOnceꢀaꢀbankꢀ
has been precharged, it is in the idle state and must be
activatedꢀpriorꢀtoꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀbeingꢀ
issued to that bank.
RAS, in conjunction with CAS and WE , forms the device
command.ꢀSeeꢀtheꢀ“CommandꢀTruthꢀTable”ꢀitemꢀforꢀdetailsꢀ
on device commands.
AUTO PRECHARGE
WE , in conjunction with RAS and CAS , forms the device
command.ꢀSeeꢀtheꢀ“CommandꢀTruthꢀTable”ꢀitemꢀforꢀdetailsꢀ
on device commands.
TheꢀAUTOꢀPRECHARGEꢀfunctionꢀensuresꢀthatꢀtheꢀpre-
charge is initiated at the earliest valid stage within a burst.
Thisꢀfunctionꢀallowsꢀforꢀindividual-bankꢀprechargeꢀwithoutꢀ
requiringꢀanꢀexplicitꢀcommand.ꢀꢀA10ꢀtoꢀenablesꢀtheꢀAUTOꢀ
PRECHARGEꢀfunctionꢀinꢀconjunctionꢀwithꢀaꢀspecificꢀREADꢀ
orꢀWRITEꢀcommand.ꢀꢀForꢀeachꢀindividualꢀREADꢀorꢀWRITEꢀ
command, auto precharge is either enabled or disabled.
VDDq is the output buffer power supply.
VDD is the device internal power supply.
GNDq is the output buffer ground.
GNDꢀisꢀtheꢀdeviceꢀinternalꢀground.
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
03/19/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
