欢迎访问ic37.com |
会员登录 免费注册
发布采购

IC42S16400F-6TL 参数 Datasheet PDF下载

IC42S16400F-6TL图片预览
型号: IC42S16400F-6TL
PDF下载: 下载PDF文件 查看货源
内容描述: 1梅格位×16位× 4银行( 64兆位)同步动态RAM [1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM]
分类和应用: 存储内存集成电路光电二极管动态存储器时钟
文件页数/大小: 55 页 / 822 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
 浏览型号IC42S16400F-6TL的Datasheet PDF文件第1页浏览型号IC42S16400F-6TL的Datasheet PDF文件第3页浏览型号IC42S16400F-6TL的Datasheet PDF文件第4页浏览型号IC42S16400F-6TL的Datasheet PDF文件第5页浏览型号IC42S16400F-6TL的Datasheet PDF文件第6页浏览型号IC42S16400F-6TL的Datasheet PDF文件第7页浏览型号IC42S16400F-6TL的Datasheet PDF文件第8页浏览型号IC42S16400F-6TL的Datasheet PDF文件第9页  
IS42S16400F  
IC42S16400F  
GENERAL DESCRIPTION  
Theꢀ 64Mbꢀ SDRAMꢀ isꢀ aꢀ highꢀ speedꢀ CMOS,ꢀ dynamicꢀ  
random-accessꢀ memoryꢀ designedꢀ toꢀ operateꢀ inꢀ 3.3Vꢀ  
memoryꢀsystemsꢀcontainingꢀ67,108,864ꢀbits.ꢀꢀInternallyꢀ  
configuredasaquad-bankDRAMwithasynchronousꢀ  
interface.Each16,777,216-bitbankisorganizedas4,096ꢀ  
rows by 256 columns by 16 bits.  
otherthreebankswillhidetheprechargecyclesandprovide  
seamless, high-speed, random-access operation.  
SDRAM readandwriteaccessesareburstorientedstarting  
at a selected location and continuing for a programmed  
numberꢀ ofꢀ locationsꢀ inꢀ aꢀ programmedꢀ sequence.ꢀ Theꢀ  
registrationꢀ ofꢀ anꢀ ACTIVEꢀ commandꢀ beginsꢀ accesses,ꢀ  
followedbyaREADorꢀWRITEꢀcommand.ꢀTheꢀACTIVEꢀ  
command in conjunction with address bits registered are  
usedtoselectthebankandrowtobeaccessed(BA0,ꢀ  
BA1ꢀselectꢀtheꢀbank;ꢀA0-A11ꢀselectꢀtheꢀrow).ꢀꢀTheꢀREADꢀ  
orWRITEꢀ commandsꢀ inꢀ conjunctionꢀ withꢀ addressꢀ bitsꢀ  
registered are used to select the starting column location  
for the burst access.  
Theꢀ64MbꢀSDRAMꢀincludesꢀanꢀAUTOꢀREFRESHꢀMODE,ꢀ  
and a power-saving, power-down mode. All signals are  
registeredꢀonꢀtheꢀpositiveꢀedgeꢀofꢀtheꢀclockꢀsignal,ꢀCLK.ꢀ  
AllꢀinputsꢀandꢀoutputsꢀareꢀLVTTLꢀcompatible.  
Theꢀ64MbꢀSDRAMꢀhasꢀtheꢀabilityꢀtoꢀsynchronouslyꢀburstꢀ  
data at a high data rate with automatic column-address  
generation, theabilitytointerleavebetweeninternalbanks  
to hide precharge time and the capability to randomly  
change column addresses on each clock cycle during  
burst access.  
ProgrammableꢀREADꢀorꢀWRITEꢀburstꢀlengthsꢀconsistꢀofꢀ  
1, 2, 4 and 8 locations, or full page, with a burst terminate  
option.  
A self-timed row precharge initiated at the end of the burst  
sequenceisavailablewiththeAUTOPRECHARGEfunctionꢀ  
enabled. Precharge one bank while accessing one of the  
FUNCTIONAL BLOCK DIAGRAM  
CLK  
CKE  
CS  
RAS  
CAS  
WE  
DQM  
DATA IN  
BUFFER  
COMMAND  
DECODER  
&
CLOCK  
GENERATOR  
16  
16  
REFRESH  
CONTROLLER  
MODE  
REGISTER  
DQ 0-15  
A10  
12  
V
DD/VDDQ  
SELF  
DATA OUT  
BUFFER  
REFRESH  
GND/GNDQ  
A11  
CONTROLLER  
16  
16  
A9  
A8  
A7  
A6  
REFRESH  
COUNTER  
A5  
A4  
4096  
A3  
A2  
A1  
A0  
BA0  
BA1  
4096  
MEMORY CELL  
ARRAY  
4096  
4096  
12  
BANK 0  
ROW  
ADDRESS  
LATCH  
ROW  
ADDRESS  
BUFFER  
12  
12  
SENSE AMP I/O GATE  
256K  
(x 16)  
COLUMN  
ADDRESS LATCH  
BANK CONTROL LOGIC  
8
BURST COUNTER  
COLUMN DECODER  
COLUMN  
ADDRESS BUFFER  
8
2
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. A  
03/19/08