providedꢀthatꢀautoꢀprechargeꢀwasꢀnotꢀactivated.TheꢀBURSTꢀ
IS42S16400F
IC42S16400F
diagramꢀforꢀeachꢀpossibleꢀCASꢀlatency;ꢀdataꢀelementꢀn +ꢀ
3 is either the last of a burst of four or the last desired of
aꢀlongerꢀburst.ꢀFollowingꢀtheꢀPRECHARGEꢀcommand,ꢀaꢀ
subsequent command to the same bank cannot be issued
until tr p is met. Note that part of the row precharge time is
hidden during the access of the last data element(s).
Full-pageꢀREADꢀburstsꢀcanꢀbeꢀtruncatedꢀwithꢀtheꢀBURSTꢀ
TERMINATEꢀ command,ꢀ andꢀ fixed-lengthꢀ READꢀ burstsꢀ
mayꢀbeꢀtruncatedꢀwithꢀaꢀBURSTꢀTERMINATEꢀcommand,ꢀ
TERMINATEꢀcommandꢀshouldꢀbeꢀissuedꢀx cycles before
the clock edge at which the last desired data element is
valid, where x equalsꢀtheꢀCASꢀlatencyꢀminusꢀone.ꢀThisꢀisꢀ
shownꢀinꢀtheꢀREADꢀBurstꢀTerminationꢀdiagramꢀforꢀeachꢀ
possibleꢀCASꢀlatency;ꢀdataꢀelementꢀn+ꢀ3ꢀisꢀtheꢀlastꢀdesiredꢀ
data element of a longer burst.
Inꢀ theꢀ caseꢀ ofꢀ aꢀ fixed-lengthꢀ burstꢀ beingꢀ executedꢀ toꢀ
completion,ꢀ aꢀ PRECHARGEꢀ commandꢀ issuedꢀ atꢀ theꢀ
optimum time (as described above) provides the same
operationꢀ thatꢀ wouldꢀ resultꢀ fromꢀ theꢀ sameꢀ fixed-lengthꢀ
burstꢀwithꢀautoꢀprecharge.ꢀTheꢀdisadvantageꢀofꢀtheꢀPRE-
CHARGEꢀcommandꢀisꢀthatꢀitꢀrequiresꢀthatꢀtheꢀcommandꢀ
and address buses be available at the appropriate time to
issueꢀtheꢀcommand;ꢀtheꢀadvantageꢀofꢀtheꢀPRECHARGEꢀ
commandꢀisꢀthatꢀitꢀcanꢀbeꢀusedꢀtoꢀtruncateꢀfixed-lengthꢀ
or full-page bursts.
CAS Latency
T0
T1
T2
T3
CLK
READ
NOP
NOP
COMMAND
DQ
t
AC
D
OUT
OH
t
LZ
t
CAS Latency - 2
T0
T1
T2
T3
T4
CLK
READ
NOP
NOP
NOP
COMMAND
DQ
tAC
D
OUT
OH
t
LZ
t
CAS Latency - 3
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Integrated Silicon Solution, Inc. — www.issi.com
21
Rev. A
03/19/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
