IS42S16100E, IC42S16100E
Write Cycle / Clock Suspend
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
tCKS
CL
tCKH
t
t
CK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMN m
AUTO PRE
ROW
ROW
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
t
AH
AH
ROW
A10
A11
NO PRE
BANK 1
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
t
CH
tCS
DQM
DQ
t
DS
tDS
t
DH
tDH
DIN
m
DIN m+1
tRCD
tDPL
t
RAS
t
RAS
RC
tRP
t
t
RC
<SPND
>
<
PRE
>
<
ACT>
<
WRIT, SPND
>
<ACT >
WRITA, SPND
PALL
Undefined
Don't Care
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don’t Care.
54
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08