IS42S16100E, IC42S16100E
Write Cycle / Byte Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
t
CL
tCK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMN m
AUTO PRE
ROW
ROW
ROW
A0-A9
t
BANK 0 AND 1
BANK 0 OR 1
t
t
AH
AH
ROW
A10
A11
NO PRE
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
tCH
tCS
UDQM
tCS
t
CH
LDQM
DQ8-15
DQ0-7
t
t
DS
tDH
t
DH
t
DS
DH
tDS
D
IN
m
m
D
IN m+1
D
IN m+3
t
DS
t
DH
t
DS
tDH
D
IN
DIN m+3
t
RCD
tDPL
t
RCD
RAS
RC
t
RAS
RC
t
RP
t
t
t
<
PRE
PALL
>
<
ACT>
<
WRIT
WRITA
>
<
MASKL
>
<ACT>
<MASK
>
<ENB>
<
>
<
>
Undefined
Don't Care
CAS latency = 2, burst length = 4
Note 1: A8,A9 = Don’t Care.
58
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
