IS42S16100E, IC42S16100E
Read Cycle / Clock Suspend
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
tCS
tCKS
tCKH
tCL
tCK
CKE
CS
tCKA
tCH
tCS
tCS
tCS
tAS
tAS
tCH
tCH
tCH
tAH
RAS
CAS
WE
(1)
COLUMN m
AUTO PRE
ROW
ROW
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
tAH
tAH
ROW
A10
A11
NO PRE
BANK 1
tAS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
tCH
tAC
tCS
tQMD
DQM
DQ
tAC
tOH
tOH
D
OUT
m
DOUT m+1
tLZ
tHZ
tRCD
tRAS
tCAC
tRAS
tRC
tRP
tRC
<SPND>
<SPND>
<PRE>
<ACT 0>
<READ>
<ACT >
<PALL>
Undefined
Don't Care
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com
53
Rev. C
01/22/08