IS42S16100E, IC42S16100E
Read Cycle / Byte Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
t
CKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
t
t
AS
AS
tAH
COLUMN m
AUTO PRE
ROW
ROW
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
t
AH
AH
ROW
A10
A11
NO PRE
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
t
CH
t
CS
t
QMD
UDQM
tQMD
tCS
t
CH
LDQM
t
t
AC
t
HZ
t
AC
t
AC
t
OH
tOH
t
LZ
t
OH
t
LZ
DQ8-15
D
OUT
m
D
OUT m+2
DOUT m+3
AC
t
t
AC
t
OH
tOH
LZ
D
OUT m+1
DOUT
m
DQ0-7
t
RCD
t
CAC
t
QMD
t
RQL
t
RCD
RAS
RC
t
RAS
RC
t
RP
t
t
t
<
PRE>
<
ACT>
<
READ
READA
>
<MASKU
>
<ACT>
<
ENBU, MASKL
>
<MASKL>
<
PALL>
<
>
Undefined
Don't Care
CAS latency = 2, burst length = 4
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com
57
Rev. C
01/22/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
