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IC41C8512-35KI 参数 Datasheet PDF下载

IC41C8512-35KI图片预览
型号: IC41C8512-35KI
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM, 512KX8, 35ns, CMOS, PDSO28, 0.400 INCH, SOJ-28]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 21 页 / 202 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IC41C8512  
IC41LV8512  
Functional Description  
The IC41C8512 and IC41LV8512 is a CMOS DRAM  
optimized for high-speed bandwidth, low power applica-  
tions. During READ or WRITE cycles, each bit is uniquely  
addressed through the 10 address bits. These are entered  
10 bits (A0-A9) at a time. The row address is latched by the  
Row Address Strobe (RAS). The column address is latched  
by the Column Address Strobe (CAS) . RAS is used to latch  
the first ten bits and CAS is used to latch the latter nine bits.  
Refresh Cycle  
To retain data, 1024 refresh cycles are required in each  
16 ms period. There are two ways to refresh the memory.  
1. By clocking each of the 1024 row addresses (A0 through  
A9) with RAS at least once every 16 ms. Any read, write,  
read-modify-write or RAS-only cycle refreshes the ad-  
dressed row.  
2. Using a CAS-before-RAS refresh cycle. CAS-before-  
RAS refresh is activated by the falling edge of RAS,  
while holding CAS LOW. In CAS-before-RAS refresh  
cycle, an internal 10-bit counter provides the row ad-  
dresses and the external address inputs are ignored.  
Memory Cycle  
A memory cycle is initiated by bring RAS LOW and it is  
terminated by returning both RAS and CAS HIGH. To  
ensures proper device operation and data integrity any  
memory cycle, once initiated, must not be ended or  
aborted before the minimum tRAS time has expired. A new  
cycle must not be initiated until the minimum precharge  
time tRP, tCP has elapsed.  
CAS-before-RAS is a refresh-only mode and no data  
access or device selection is allowed. Thus, the output  
remains in the High-Z state during the cycle.  
Extended Data Out Page Mode  
EDO page mode operation permits all 1024 columns within  
a selected row to be randomly accessed at a high data rate.  
Read Cycle  
A read cycle is initiated by the falling edge of CAS or OE,  
whichever occurs last, while holding WE HIGH. The  
column address must be held for a minimum time specified  
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC  
and tOE are all satisfied. As a result, the access time is  
dependent on the timing relationships between these  
parameters.  
In EDO page mode read cycle, the data-out is held to the  
next CAS cycle’s falling edge, instead of the rising edge.  
For this reason, the valid data output time in EDO page  
mode is extended compared with the fast page mode. In  
the fast page mode, the valid data output time becomes  
shorter as the CAS cycle time becomes shorter. Therefore,  
in EDO page mode, the timing margin in read cycle is  
larger than that of the fast page mode even if the CAS cycle  
time becomes shorter.  
Write Cycle  
A write cycle is initiated by the falling edge of CAS and  
WE, whichever occurs last. The input data must be valid  
at or before the falling edge of CAS or WE, whichever  
occurs first.  
In EDO page mode, due to the extended data function, the  
CAS cycle time can be shorter than in the fast page mode  
if the timing margin is the same.  
The EDO page mode allows both read and write opera-  
tions during one RAS cycle, but the performance is  
equivalent to that of the fast page mode in that case.  
Power-On  
After application of the VCC supply, an initial pause of  
200 µs is required followed by a minimum of eight initial-  
ization cycles (any combination of cycles containing a  
RAS signal).  
During power-on, it is recommended that RAS track with  
VCC or be held at a valid VIH to avoid current surges.  
Integrated Circuit Solution Inc.  
DR029-0A 09/28/2001  
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