IC41C8512
IC41LV8512
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
35
Min. Max.
-50
-60
Symbol
Parameter
Min. Max.
Min. Max.
Units
tACH
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
15
—
15
—
15
—
ns
tOEH
OE Hold Time from WE during
8
—
10
—
15
—
ns
READ-MODIFY-WRITE cycle(18)
tDS
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
0
6
—
—
—
—
0
8
—
—
—
—
0
—
—
—
—
ns
ns
ns
ns
tDH
10
tRWC
tRWD
READ-MODIFY-WRITE Cycle Time
80
45
125
70
140
80
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle(14)
tCWD
tAWD
tPC
CAS to WE Delay Time(14, 20)
25
30
12
—
—
—
34
42
20
—
—
—
36
49
25
—
—
—
ns
ns
ns
Column-Address to WE Delay Time(14)
EDO Page Mode READ or WRITE
Cycle Time(24)
tRASP
tCPA
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge(15)
35 100K
50 100K
50 100K
ns
ns
ns
—
40
21
—
—
47
27
—
—
56
34
—
tPRWC
EDO Page Mode READ-WRITE
Cycle Time(24)
tCOH
tOFF
Data Output Hold after CAS LOW
5
3
—
15
5
3
—
15
5
3
—
15
ns
ns
Output Buffer Turn-Off Delay from
(13,15,19, 29)
CAS or RAS
tWHZ
Output Disable Delay from WE
3
15
—
3
15
—
3
15
—
ns
ns
tCLCH
Last CAS going LOW to First CAS
10
10
10
returning HIGH(23)
tCSR
tCHR
tORD
CAS Setup Time (CBR REFRESH)(30, 20)
8
8
0
—
—
—
10
10
0
—
—
—
10
10
0
—
—
—
ns
ns
ns
CAS Hold Time (CBR REFRESH)(30, 21)
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
tREF
tT
Refresh Period (512 Cycles)
Transition Time (Rise or Fall)(2, 3)
—
1
8
8
1
—
50
8
1
—
50
ms
ns
50
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)
One TTL Load and 50 pF (Vcc = 3.3V ±10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
9
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
