IC41C1665
IC41LV1665
ELECTRICAL CHARACTERISTICS(1) (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max.
Unit
IIL
Input Leakage Current
Any input 0V ≤ VIN ≤ Vcc
–10
10
µA
Other inputs not under test = 0V
IIO
Output Leakage Current
Output is disabled (Hi-Z)
–10
10
µA
0V ≤ VOUT ≤ Vcc
VOH
VOL
Output High Voltage Level
Output Low Voltage Level
IOH = –5 mA
2.4
—
—
V
V
IOL = +4.2 mA
0.4
ICC1
Stand-by Current: TTL
RAS, LCAS, UCAS ≥ VIH
5V
—
2
mA
mA
mA
mA
mA
mA
mA
ICC1
Stand-by Current: TTL
RAS, LCAS, UCAS ≥ VIH
3.3V
—
1
ICC2
ICC2
ICC3
Stand-by Current: CMOS
Stand-by Current: CMOS
RAS, LCAS, UCAS ≥ VCC – 0.2V
RAS, LCAS, UCAS ≥ VCC – 0.2V
RAS, LCAS, UCAS,
Address Cycling, tRC = tRC (min.)
5V
—
—
1
3.3V
0.5
OperatingCurrent:
-25
-30
—
—
170
150
RandomRead/Write(2,3,4)
Average Power Supply Current
-35
-40
—
—
130
120
ICC4
OperatingCurrent:
RAS = VIL, LCAS, UCAS,
-25
-30
-35
—
—
—
170
150
130
mA
mA
mA
Fast Page Mode(2,3,4)
Cycling tPC = tPC (min.)
Average Power Supply Current
-40
—
120
ICC5
Refresh Current:
RAS Cycling, LCAS, UCAS ≥ VIH
tRC = tRC (min.)
-25
-30
-35
—
—
—
170
150
130
RAS-Only(2,3)
Average Power Supply Current
-40
—
120
ICC6
Refresh Current:
RAS, LCAS, UCAS Cycling
tRC = tRC (min.)
-25
-30
-35
—
—
—
170
150
130
CBR(2,3,5)
Average Power Supply Current
-40
—
120
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper
device operation is assured.The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is
exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each fast page cycle.
5. Enables on-chip refresh and address counters.
Integrated Circuit Solution Inc.
DR031-0A 10/17/2001
7
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
