IC41C1665
IC41LV1665
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-25
-30
Min. Max.
-35
-40
Symbol Parameter
tACH
Min. Max.
Min. Max.
Min. Max.
Units
ns
Column-Address Setup Time to CAS
15
—
15
—
15
—
15
—
Precharge during WRITE Cycle
tOEH
OE Hold Time from WE during
4
—
4
—
4
—
5
—
ns
READ-MODIFY-WRITEcycle(18)
tDS
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
0
5
—
—
—
—
0
5
—
—
—
—
0
5
—
—
—
—
0
5
—
—
—
—
ns
ns
ns
ns
tDH
tRWC
tRWD
READ-MODIFY-WRITECycleTime
65
34
85
46
95
51
105
56
RAS to WE Delay Time during
READ-MODIFY-WRITECycle(14)
tCWD
tAWD
tPC
CAS to WE Delay Time(14, 20)
17
21
15
—
—
—
25
32
20
—
—
—
26
34
23
—
—
—
27
36
25
—
—
—
ns
ns
ns
Column-Address to WE Delay Time(14)
Fast Page Mode READ or WRITE
CycleTime(24)
tRASP
tCPA
Fast Page Mode RAS Pulse Width
Access Time from CAS Precharge(15)
Fast Page Mode READ-WRITE Cycle Time(24)
Output Buffer Turn-Off Delay from
25
—
37
3
10k
14
—
15
30
—
42
3
10K
18
35
—
49
3
10K
20
—
15
40
—
52
3
10K
22
ns
ns
ns
ns
tPRWC
tOFF
—
15
—
15
(13,15,19, 29)
CAS or RAS
tCLCH
Last CAS going LOW to First CAS
4
—
9
—
10
—
11
—
ns
returning HIGH(23)
tCSR
tCHR
tORD
CAS Setup Time (CBR REFRESH)(30, 20)
5
7
0
—
—
—
10
10
0
—
—
—
10
10
0
—
—
—
10
10
0
—
—
—
ns
ns
ns
CAS Hold Time (CBR REFRESH)(30, 21)
OE Setup Time prior to RAS during
HIDDENREFRESHCycle
tREF
tT
Refresh Period (256 Cycles)
Transition Time (Rise or Fall)(2, 3)
—
4
—
4
—
4
—
4
ms
ns
1
50
1
50
1
50
1
50
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)
One TTL Load and 50 pF (Vcc = 3.3V ±10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
Integrated Circuit Solution Inc.
DR031-0A 10/17/2001
9
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
