ISL88731A
takes control of the output (assuming that the adapter
60
40
20
0
current is below the limit set by ACLIM). The voltage error
amplifier (GMV) discharges the capacitor on VCOMP to limit
the output voltage. The current to the battery decreases as
the cells charge to the fixed voltage and the voltage across
the internal battery resistance decreases. As battery current
decreases the two current error amplifiers (GMI and GMS)
output their maximum current and charge the capacitor on
ICOMP to its maximum voltage (limited to 0.3V above
VCOMP). With high voltage on ICOMP, the minimum voltage
buffer output equals the voltage on VCOMP.
Compensator
Modulator
Loop
F
ZERO
-20
-40
-60
F
F
F
The voltage control loop is shown in Figure 23.
FILTER
POLE1
L
PHASE
POLE2
11
RFET_RDSON
RL_DCR
0.01
0.1
1
10
100
1000
FREQUENCY (kHz)
CA2
FIGURE 21. CHARGE CURRENT LOOP BODE PLOTS
RF2
+
0.25
CSOP
CSON
Σ
S
+
-
20x
CF2
RS2
-
DCIN
R3
VCOMP
L
RBAT
PHASE
RFET_RDSON
-
GMV
+
RS1
CO
RESR
11
R4
RL_DCR
RF1
CVCOMP
RVCOMP
DACV
CF1
CA2
RF2
CSOP
CSON
+
0.25
+
S
Σ
20X
-
CF2
RS2
-
FIGURE 23. VOLTAGE CONTROL LOOP
CSSN
CSSP
-
+
20
Output LC Filter Transfer Functions
CO
RBAT
CA1
The gain from the phase node to the system output and
RESR
battery depend entirely on external components. Typical
output LC filter response is shown in Figure 24. Transfer
function ALC(s) is shown in Equation 22:
-
+
GMS
DACS
ICOMP
CICOMP
s
⎛
⎝
⎞
⎠
---------------
1 –
ω
ESR
FIGURE 22. ADAPTER CURRENT LIMIT CONTROL LOOP
----------------------------------------------------------
A
=
LC
2
⎛
⎜
⎝
⎞
s
ω
s
----------- ------------------------
+
+ 1
⎟
The loop response equations, bode plots and the selection
of CICOMP are the same as the charge current control loop
with loop gain reduced by the duty cycle and the ratio of
(ω ⋅ Q)
LC
⎠
DP
1
L
C
o
1
-----------------------
ω
=
Q = R
⋅
------
--------------------------------
ω
=
LC
o
ESR
(R
⋅ C )
( L ⋅ C )
R
/R . In other words, if R = R and the duty cycle
ESR
o
o
S1 S2 S1 S2
D = 50%, the loop gain will be 6dB lower than the loop gain
in Figure 22. This gives lower crossover frequency and
(EQ. 22)
higher phase margin in this mode. If R /R = 2 and the
The resistance RO is a combination of MOSFET r ,
DS(ON)
S1 S2
duty cycle is 50% then the adapter current loop gain will be
identical to the gain in Figure 22.
inductor DCR, R
and the internal resistance of the
SENSE
battery (normally between 50mΩ and 200mΩ) The worst
case for voltage mode control is when the battery is absent.
This results in the highest Q of the LC filter and the lowest
phase margin.
A filter should be added between RS1 and CSIP and CSIN to
reduce switching noise. The filter roll off frequency should be
between the crossover frequency and the switching
frequency (~100kHz).
The compensation network consists of the voltage error
amplifier GMV and the compensation network R
,
VCOMP
Voltage Control Loop
C
which give the loop very high DC gain, a very low
VCOMP
frequency pole and a zero at F
When the battery is charged to the voltage set by
ChargeVoltage register the voltage error amplifier (GMV)
. Inductor current
ZERO1
FN6738.0
July 23, 2008
19
INTERSIL [ Intersil ]
