FIGURE 5. LASI EQUIVALENT SCHEMATIC
(See Also Figure 4)
OPTX
LBC
OPT
OPTX
LOP
TX_
REG 1.9005h[3:0]
LASI STATUS
TEMP
FAULT
REG.
4.C00Ah.
3:0
REG.
4.C007h.
11:8
REG.
4.C007h.
7:4
REG.
REG
REG 1.C01Dh.2:0
4.24.3:0
1.C012h.13
POLARITY
ALARM PIN POLARITY
Q
D
LS ALARM
REG. 3.24.12
REG. 1.10.0
REG. 4.24.12
Clock on
any
LS_ALARM
Masked
LINK
CLK
STATUS
change
PHY XS
LOS
PHY XS
FIFO
PHY XS
CODE
PHY XS
BYTE
CLR
(SIG DET)
ERROR
ERROR
SYNCH
Clear on Read of 1.9005
REG 1.9006h[7:0]
TX_FLAG CONTROL
See IEEE
TX_FLAG
REG 1.A070h[7:0]
TX_FLAG
Latch on high
REGISTER 1.9004h.[10:0] TX_ALARM_STATUS
Clear on read
TX ALARM
Masked
TX_ALARM
REGISTER 1.9001h[10:0] TX_ALARM CONTROL
REGISTER 1.9000h[6:0] RX_ALARM CONTROL
LASI
RX_ALARM
RX ALARM
Masked
Clear on read
REGISTER 1.9003h.[6:0] RX_ALARM_STATUS
Latch on high
REG 1.C012h.[4:0]
GPIO-LASI EN
REG 1.C012h.[12:8]
GPIO POLARITY
GPIO
GPIO->LASI
Latch
hi
PCS
ALARM
Masked
BYTE
SYNCH
GPIO
[4:0]
REG 1.9002h[3:0]
LASI CONTROL
REG
3.24
[3:0]
LX4
CX4
Selector for
PCS
CODE
ERROR
PCS
FIFO
CX4 vs LX4
ERROR
REG 1.9007h[7:6]
RX_FLAG CONTROL
LASI
External Pad
REG
REG.
3.C007h.
7:4
REG.
3.C007h.
11:8
RX_FLAG
1.C01Dh.3
REG 1.A074h[7:6]
RX_FLAG
OPRX
OP
Legend
INTERSIL [ Intersil ]
