ISL23428
The first part starts by HIGH-to-LOW transition on CS line,
Applications Information
Communicating with ISL23428
Communication with ISL23428 proceeds using SPI interface
through the ACR (address 10000b), WR0 (addresses 00000b)
and WR1 (addresses 00001b) registers.
followed by N two bytes read instruction on SDI line with reversed
chain access sequence: the instruction byte + dummy data byte
for the last DCP in chain is going first, followed by LOW-to-HIGH
transition on CS line. The read instructions are executed during
the second part of read sequence. It also starts by HIGH-to-LOW
transition on CS line, followed by N number of two bytes NOP
instructions on SDI line and LOW-to-HIGH transition of CS. The
data is read on every even byte during the second part of the
read sequence while every odd byte contains code 111b followed
by address from which the data is being read.
The wiper of the potentiometer is controlled by the WRi register.
Writes and reads can be made directly to these registers to
control and monitor the wiper position.
Daisy Chain Configuration
Wiper Transition
When an application needs more than one ISL23428, it can
communicate with all of them without additional CS lines by
daisy chaining the DCPs as shown in Figure 29. In Daisy Chain
configuration, the SDO pin of the previous chip is connected to
the SDI pin of the following chip, and each CS and SCK pins are
connected to the corresponding microcontroller pins in parallel,
like regular SPI interface implementation. The Daisy Chain
configuration can also be used for simultaneous setting of
multiple DCPs. Note, the number of daisy chained DCPs is
limited only by the driving capabilities of the SCK and CS pins of
the microcontroller; for larger number of SPI devices, buffering of
SCK and CS lines is required.
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the sudden
transition from a very low impedance “make” to a much higher
impedance “break” within a short period of time (<1µs). There
are several code transitions such as 0Fh to 10h, 1Fh to 20h,...,
6Fh to 7Fh, which have higher transient glitch. Note that all
switching transients will settle well within the settling time as
stated in the datasheet. A small capacitor can be added
externally to reduce the amplitude of these voltage transients,
but that will also reduce the useful bandwidth of the circuit, thus
this may not be a good solution for some applications. It may be
a good idea, in that case, to use fast amplifiers in a signal chain
for fast recovery.
Daisy Chain Write Operation
The write operation starts by HIGH-to-LOW transition on CS line,
followed by N number of two bytes write instructions on SDI line
with reversed chain access sequence: the instruction byte + data
byte for the last DCP in chain is going first, as shown in Figure 30,
where N is a number of DCPs in chain. The serial data is going
through DCPs from DCP0 to DCP(N-1) as follows: DCP0 --> DCP1 -->
DCP2 --> ... --> DCP(N-1). The write instruction is executed on the
rising edge of CS for all N DCPs simultaneously.
V
Requirements
LOGIC
It is recommended to keep V
normal operation. In a case where turning V
LOGIC
necessary, it is recommended to ground the V
ISL23428. Grounding the V
not affect other devices on the same bus. It is good practice to put
a 1µF capacitor in parallel with 0.1µF decoupling capacitor close to
powered all the time during
OFF is
pin of the
LOGIC
LOGIC
and V does
pin or both V
LOGIC
LOGIC
CC
Daisy Chain Read Operation
the V pin.
LOGIC
The read operation consists of two parts: first, send the read
instructions (N two bytes operation) with valid address; second,
read the requested data while sending NOP instructions (N two
bytes operation) as shown in Figures 31 and 32.
V
Requirements and Placement
CC
It is recommended to put a 1µF capacitor in parallel with 0.1µF
decoupling capacitor close to the V pin.
CC
N DCP IN A CHAIN
CS
SCK
DCP0
DCP1
DCP2
DCP(N-1)
CS
MOSI
MISO
CS
CS
CS
SCK
SDI
SCK
SDI
SCK
SDI
SCK
SDI
µC
SDO
SDO
SDO
SDO
FIGURE 29. DAISY CHAIN CONFIGURATION
FN7904.0
August 25, 2011
17
INTERSIL [ Intersil ]
