28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 2. 3 Volt Advanced Boot Block Pin Descriptions
Symbol
Type
Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or
erase cycle.
A –A
INPUT
28F004B3: A[0-18], 28F008B3: A[0-19], 28F016B3: A[0-20],
28F400B3: A[0-17], 28F800B3: A[0-18], 28F160B3: A[0-19],
28F320B3: A[0-20], 28F640B3: A[0-21]
0
21
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program
INPUT/
command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is
DQ –DQ
0
7
OUTPUT internally latched. Outputs array, identifier and status register data. The data pins float to tri-state when
the chip is de-selected or the outputs are disabled.
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program
command. Data is internally latched. Outputs array and identifier data. The data pins float to tri-state
when the chip is de-selected. Not included on x8 products.
DQ –
INPUT/
OUTPUT
8
DQ
15
CHIP ENABLE: Activates the internal control logic, input buffers, decoders and sense amplifiers. CE#
CE#
INPUT
is active low. CE# high de-selects the memory device and reduces power consumption to standby
levels.
OUTPUT ENABLE: Enables the device’s outputs through the data buffers during a read operation.
OE# is active low.
OE#
WE#
INPUT
INPUT
WRITE ENABLE: Controls writes to the Command Register and memory array. WE# is active low.
Addresses and data are latched on the rising edge of the second WE# pulse.
RESET/DEEP POWER-DOWN: Uses two voltage levels (V , V ) to control reset/deep power-down
IL
IH
mode.
When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs
to High-Z, resets the Write State Machine, and minimizes current levels (I ).
RP#
INPUT
CCD
When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-
low to logic-high, the device defaults to the read array mode.
WRITE PROTECT: Provides a method for locking and unlocking the two lockable parameter blocks.
When WP# is at logic low, the lockable blocks are locked, preventing program and erase
operations to those blocks. If a program or erase operation is attempted on a locked block, SR.1 and
either SR.4 [program] or SR.5 [erase] will be set to indicate the operation failed.
WP#
INPUT
INPUT
When WP# is at logic high, the lockable blocks are unlocked and can be programmed or erased.
See Section 3.3 for details on write protection.
OUTPUT V : Enables all outputs to be driven to 1.8 V – 2.5 V while the V is at 2.7 V–3.3 V. If the
CC
CC
V
is regulated to 2.7 V–2.85 V, V
can be driven at 1.65 V–2.5 V to achieve lowest power
CC
CCQ
V
V
CCQ
CC
operation (see Section 4.4).
This input may be tied directly to V (2.7 V–3.6 V).
CC
DEVICE POWER SUPPLY: 2.7 V–3.6 V
PROGRAM/ERASE POWER SUPPLY: Supplies power for program and erase operations. V may
PP
be the same as V (2.7 V–3.6 V) for single supply voltage operation. For fast programming at
CC
manufacturing, 11.4 V–12.6 V may be supplied to V . This pin cannot be left floating. Applying
PP
11.4 V–12.6 V to V can only be done for a maximum of 1000 cycles on the main blocks and 2500
PP
V
PP
cycles on the parameter blocks. V may be connected to 12 V for a total of 80 hours maximum (see
PP
Section 3.4 for details).
V
< V
protects memory contents against inadvertent or unintended program and erase
PPLK
PP
commands.
GND
NC
GROUND: For all internal circuitry. All ground inputs must be connected.
NO CONNECT: Pin may be driven or left floating.
6
3UHOLPLQDU\
INTEL [ INTEL ]
