28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 2. 48-Lead TSOP Package for x16 Configurations
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VCCQ
GND
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
A8
64 M
32 M
A21
A20
WE#
RP#
VPP
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
Advanced Boot Block
48-Lead TSOP
12 mm x 20 mm
TOP VIEW
16 M
0580_02
NOTE: Lower densities will have NC on the upper address pins. For example, an 16-Mbit device will have NC
on Pins 9 and 10.
Figure 3. x8 48-Ball µBGA* Chip Size Package (Top View, Ball Down)
1
2
3
4
5
6
7
8
16M
A
B
C
D
E
F
A14
A12
A8
VPP
WP#
A20
A7
A4
8M
A15
A10
A13
NC
A11
D7
WE#
A9
RP#
A19
A18
A5
A3
A2
A1
A16
A6
A17
D5
NC
NC
D4
D2
D3
NC
NC
NC
CE#
D0
A0
VCCQ
GND
D6
GND
OE#
NC
VCC
D1
0580_04
NOTES:
1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the
upper address solder balls. Routing is not recommended in this area. A is the upgrade address for the
20
16-Mbit device.
2. 4-Mbit density not available in µBGA* CSP.
4
3UHOLPLQDU\
INTEL [ INTEL ]
