256-Mbit J3 (x8/x16)
Figure 25. Clear Lock-Bit Flowchart
Start
Write 60H
Bus
Operation
Command
Comments
Data = 60H
Clear Block
Lock-Bits Setup
Write
Addr = X
Clear Block or
Lock-Bits Confirm
Data = D0H
Addr = X
Write
Read
Write D0H
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Read Status Register
Standby
Write FFH after the clear lock-bits operation to place device in read
array mode.
0
SR.7 =
1
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Command
Comments
Read Status Register
Data (See Above)
Check SR.3
Standby
1 = Programming Voltage Error
Detect
1
SR.3 =
0
Voltage Range Error
Check SR.4, 5
Both 1 = Command Sequence
Error
Standby
Standby
1
1
Check SR.5
1 = Clear Block Lock-Bits Error
Command Sequence
Error
SR.4,5 =
0
SR.5, SR.4, and SR.3 are only cleared by the Clear Status Register
command.
Clear Block Lock-Bits
Error
SR.5 =
0
If an error is detected, clear the status register before attempting retry
or other error recovery.
Clear Block Lock-Bits
Successful
66
Datasheet
INTEL [ INTEL ]
