256-Mbit J3 (x8/x16)
Figure 22. Block Erase Flowchart
Bus
Operation
Command
Comments
Start
Data = 20H
Addr = Block Address
Write
Erase Block
Erase
Confirm
Data = D0H
Addr = X
Write (Note 1)
Issue Single Block Erase
Command 20H, Block
Address
Status register data
With the device enabled,
OE# low updates SR
Addr = X
Read
Check SR.7
Standby
1 = WSM Ready
0 = WSM Busy
Write Confirm D0H
Block Address
1. The Erase Confirm byte must follow Erase Setup.
This device does not support erase queuing. Please see
Application note AP-646 For software erase queuing
compatibility.
Read
Status Register
Full status check can be done after all erase and write
sequences complete. Write FFH after the last operation to
reset the device to read array mode.
No
Suspend
Erase Loop
0
Yes
SR.7 =
Suspend Erase
1
Full Status
Check if Desired
Erase Flash
Block(s) Complete
0606_09
Datasheet
63
INTEL [ INTEL ]
