256-Mbit J3 (x8/x16)
7.4
Reset Operation
Figure 14. AC Waveform for Reset Operation
VIH
STS (R)
VIL
P2
VIH
RP# (P)
VIL
P1
NOTE: STS is shown in its default mode (RY/BY#).
Table 11. Reset Specifications
#
Sym
Parameter
Min
Max
Unit
Notes
RP# Pulse Low Time
P1
t
t
(If RP# is tied to V , this specification is not
applicable)
35
µs
1,2
PLPH
CC
RP# High to Reset during Block Erase, Program, or
Lock-Bit Configuration
P2
100
ns
1,3
PHRH
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not
executing then the minimum required RP# Pulse Low Time is 100 ns.
3. A reset time, t
, is required from the latter of STS (in RY/BY# mode) or RP# going high until
PHQV
outputs are valid.
7.5
AC Test Conditions
Figure 15. Transient Input/Output Reference Waveform for VCCQ = 2.7 V–3.6 V
VCCQ
Input VCCQ/2
0.0
Test Points
VCCQ/2 Output
NOTE: AC test inputs are driven at V
for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and
CCQ
output timing ends, at V
/2 V (50% of V
). Input rise and fall times (10% to 90%) < 5 ns.
CCQ
CCQ
Datasheet
29
INTEL [ INTEL ]
