256-Mbit J3 (x8/x16)
9.0
Bus Operations
This section provides an overview of device bus operations. The on-chip Write State Machine
(WSM) manages all erase and program algorithms. The system CPU provides control of all in-
system read, write, and erase operations of the device via the system bus.
Device commands are written to the CUI to control all of the flash memory device’s operations.
The CUI does not occupy an addressable memory location; it’s the mechanism through which the
flash device is controlled.
9.1
Bus Operations Overview
The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash
memory conform to standard microprocessor bus cycles.
Table 12. Bus Operations
STS
(default
mode)
Mode
RP# CE[2:0](1) OE#(2)
WE#(2) Address VPEN
Data(3)
Notes
Read Array
Output Disable
Standby
V
V
V
Enabled
Enabled
Disabled
V
V
V
X
X
X
X
X
X
D
High Z(7)
4,5,6
IH
IH
IH
IL
IH
OUT
V
High Z
High Z
X
X
IH
IH
X
X
Reset/Power-Down
Mode
V
X
X
X
X
X
X
High Z
Note 8
High Z(7)
High Z(7)
IL
See
Table 17
Read Identifier Codes
V
Enabled
V
V
IH
IL
IH
See
Table
10.3
Read Query
V
V
Enabled
Enabled
V
V
V
V
X
X
Note 9
High Z(7)
IH
IH
IL
IL
IH
Read Status (WSM off)
X
X
X
D
OUT
IH
D7 = D
OUT
Read Status (WSM on)
V
V
Enabled
Enabled
V
V
X
D[15:8] = High Z
D[6:0] = High Z
IH
IH
IL
IH
Write
V
V
V
D
IN
X
6,10,11
IH
IL
PENH
NOTES:
1. See Table 13 on page 33 for valid CE configurations.
2. OE# and WE# should never be enabled simultaneously.
3. D refers to D[7:0] if BYTE# is low and D[15:0] if BYTE# is high.
4. Refer to DC Characteristics. When V ≤ V , memory contents can be read, but not altered.
PEN
PENLK
5. X can be V or V for control and address signals, and V
or V
for V
. See DC Characteristics for V
and
IL
IH
PENLK
PENH
PEN
PENLK
V
voltages.
PENH
6. In default mode, STS is V when the WSM is executing internal block erase, program, or lock-bit configuration algorithms. It
OL
is V
when the WSM is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or
OH
reset/power-down mode.
7. High Z will be V with an external pull-up resistor.
OH
8. See Section 10.2, “Read Identifier Codes” on page 39 for read identifier code data.
9. See Section 10.3, “Read Query/CFI” on page 41 for read query data.
10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when V
is within specification.
= V
and V
CC
PEN
PENH
32
Datasheet
INTEL [ INTEL ]
