BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
E
Start
Bus
Command
Comments
Operation
Write
Write
Clear Block
Lock-Bits Setup
Data = 60H
Addr = X
Write 60H
Clear Block
Lock-Bits Confirm
Data = D0H
Addr = X
Write D0H
Read
Status Register Data
Read Status Register
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
0
SR.7 =
Write FFH after the clear block lock-bits operation to place device in
read array mode.
1
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Read Status Register
Data (See Above)
Command
Comments
Standby
Check SR.3
1 = VPP Error Detect
1
VPP Range Error
SR.3 =
0
Standby
Check SR.1
1 = Device Protect Detect
RP# = VIH
,
Master Lock-Bit Is Set
1
Device Protect Error
SR.1 =
0
Standby
Standby
Check SR.4,5
Both 1 = Command Sequence Error
1
Check SR.5
1 = Clear Block Lock Bits Error
Command Sequence
Error
SR.4,5 =
0
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
1
Clear Block Lock-Bits
Error
SR.5 =
0
Clear Block Lock-Bits
Successful
Figure 11. Clear Block Lock-Bits Flowchart
24
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