ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
13.2
Example Implementations of GPSTB-Controlled Read and
Write Ports
Figure 13. Example GPSTB Write Port (Extension Control 2 bits 4:3 are ‘10’)
Pull-up†
PD6722
Latch
(for example, ’374)
IOW*
IOW*
EXT_WR*
O7
CK
GPSTB
General-
Purpose
Outputs
SD[15:0]
SD[15:0]
(16-bit bus)
SD[15:8]
D
O0
RES
PWRGOOD
† Pull-up resistor, or set Extension Control 2 bit 2 to ‘1’ for totem-pole output.
In this mode, Extension Control 2 register bit 4 is set to ‘1’ enabling the GPSTB pin to function as
a write strobe. Writes to the respective extended index 0Ah cause the respective GPSTB to go
active (low) for the duration of the system’s IOW* pulse.
On writes, data is written to both the external latch and the internal shadow copy of the External
Data register. A read of the respective extended index 0Ah would produce the last value written to
the latch.
Connection of the ISA bus PWRGOOD signal to the external latch ensures that the latch assumes
all ‘0’s at its outputs when the PD67XX is reset.
Figure 14. Example GPSTB Read Port (Extension Control 2 bits 4:3 are ‘01’)
PD6722
Tristate Buffer
(for example, ’244)
IOR*
IOR*
EXT_RD*
Pull-up†
D7
GPSTB
General-
Purpose
Inputs
SD[15:0]
SD[15:0]
SD[15:8]
O
(16-bit bus)
D0
OE
† Pull-up resistor, or set Extension Control 2 bit 2 to ‘1’ for totem-pole output.
Datasheet
93
INTEL [ INTEL ]
