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SPD6722QCCE 参数 Datasheet PDF下载

SPD6722QCCE图片预览
型号: SPD6722QCCE
PDF下载: 下载PDF文件 查看货源
内容描述: ISA到PC卡( PCMCIA )控制器 [ISA-to-PC-Card (PCMCIA) Controllers]
分类和应用: 总线控制器微控制器和处理器PC
文件页数/大小: 138 页 / 837 K
品牌: INTEL [ INTEL ]
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ISA-to-PC-Card (PCMCIA) Controllers PD6710/22  
15.0  
DMA Operation (PD6722 only)  
15.1  
DMA Capabilities of the PD6722  
The PD6722 include support of a DMA-capable PC Card slave and the movement of DMA data to/  
from the card with the ISA bus as a DMA master.  
Only one socket at a time should be enabled for DMA transfer because the ISA bus DMA  
handshake signals are shared between both socket interfaces.  
DMA transfers to and from the DMA-capable PC Card may be 8- or 16-bit, as indicated by the size  
of the ISA bus DMA cycle.  
Note: Transfer size at socket interface is the same as transfer size on an ISA bus. For 8-bit DMA  
transfers, connect PD6722 DMA handshake signals to ISA bus DMA channels 0, 1, 2, or 3. For 16-  
bit transfers, connect PD6722 DMA handshake signals to ISA bus DMA channels 5, 6, or 7.  
15.2  
DMA-Type PC Card Cycles  
Transfer of DMA data to or from a card is achieved through use of a special DMA-type PC Card  
interface cycle. This cycle is defined to not conflict with standard PC Card memory or I/O cycles.  
A card that is DMA-capable can distinguish PC Card interface cycle types presented by the  
PD6722 according to the following table:  
Table 19. Four Card Cycle Types for DMA-Type PC Card Interface  
Function of  
-IORD/-IOWR  
Socket Interface Cycle Type  
Function of -WE/-OE  
Function of -REG  
Card Memory Read/Write  
Attribute Memory Read/Write  
Card I/O Read/Write  
Data transfer signaling  
Data transfer signaling  
Always inactive high  
Terminal count outputs  
Always inactive high  
Always inactive high  
Data transfer signaling  
Data transfer signaling  
Always inactive high  
Always low  
Low = non-DMA I/O cycle  
High = DMA cycle  
Card DMA Data Read/Write  
Note: Bits 7 and 6 of the Extension Control 1 register must be nonzero for Table 19 to be true; otherwise  
only standard PC Card cycles will be issued to the card.  
The PC Card address is also undefined during the DMA read or write cycle.  
Card DMA data read and write cycles transfer DMA data to or from a DMA-capable PC Card.  
These cycles are distinguished from normal card I/O cycles by the -REG signal being high during  
the cycle, which is an undefined condition in the PC Card Standard.  
Datasheet  
97  
 
 
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