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SPD6722QCCE 参数 Datasheet PDF下载

SPD6722QCCE图片预览
型号: SPD6722QCCE
PDF下载: 下载PDF文件 查看货源
内容描述: ISA到PC卡( PCMCIA )控制器 [ISA-to-PC-Card (PCMCIA) Controllers]
分类和应用: 总线控制器微控制器和处理器PC
文件页数/大小: 138 页 / 837 K
品牌: INTEL [ INTEL ]
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PD6710/22 ISA-to-PC-Card (PCMCIA) Controllers  
Bit 5 allows programming of the active level of GPSTB, with the default being active-low. Setting  
bit 5 to 1causes a GPSTB output to be low normally and high (active) upon external data access.  
Bit 4 controls use of the respective GPSTB pin as a write strobe for an external general-purpose  
latch. When the respective extended index is set to 0Ah and the index register is set to the  
respective 2Fh or 6Fh setting, I/O writes that access address 3E1h will result in the respective  
GPSTB signal being driven active for the duration of the ISA bus IOW* signal being driven low.  
Bit 3 controls use of the respective GPSTB pin a read strobe for an external general-purpose buffer.  
When the respective extended index is set to 0Ah and the index register is set to the respective 2Fh  
or 6Fh setting, I/O reads that access address 3E1h will result in the respective GPSTB signal being  
driven active for the duration of the ISA bus IOR* signal being driven low.  
Bit 2 cause the GPSTB output to be totem-pole instead of the default open-collector configuration.  
When GPSTB outputs are totem-pole, their highlevel is driven to the voltage of the +5Vpin,  
instead of to high-impedance.  
If neither bit 3 nor bit 4 is set, the respective GPSTB pin functions as a reserved input in a PD6722  
that is an internal pull-up to the +5Vpin. This internal pull-up is turned off whenever the GPSTB  
pin is configured as a general-purpose strobe, or when the respective sockets Pull-up Control bit is  
set to 1.  
Bits 7:6 and 1:0 are reserved and must be programmed to 0. These bits should not be used as  
scratchpad bits.  
External Data Port Access through the External Data Register  
Data to be accessed from an external read or write port is mapped to the respective External Data  
register at Extended Index 0Ah. This allows external data to be accessed as if it were a register in  
the PD67XX register set.  
To achieve this mapping, the external data ports buffer or latch data connections should be made to  
SD[15:8] of the system bus for 16-bit systems, and to SD[7:0] of the system bus for 8-bit systems.  
To support readback of data written to an external I/O port by use of a GPSTB pin, a shadow of the  
external data register exists, which is read when an I/O read is done from the external data register  
location corresponding to a GPSTB pin programmed as a write strobe.  
For more information on the Socket A and Socket B versions of this register, see the description of  
this register in External Data (PD6722 only, Socket A, Index 2Fh)on page 81 and External Data  
(PD6722 only, Socket A, Index 6Fh)on page 82.  
Register Name: External Data  
Register Per: socket  
Extended Index: 0Ah  
Bit 4 Bit 3  
Index: 2Fh  
Register Compatibility Type: ext.  
Bit 7  
Bit 6  
Bit 5  
Bit 2  
Bit 1  
Bit 0  
External Data External Data External Data External Data External Data External Data External Data External Data  
7
6
5
4
3
2
1
0
RW:0  
RW:0  
RW:0  
RW:0  
RW:0  
RW:0  
RW:0  
RW:0  
92  
Datasheet  
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