ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
13.0
Using GPSTB Pins for External Port Control
(PD6722 only)
The PD6722 provides pins that can be programmed to function as general-purpose strobes to
external latches or buffers, allowing them to serve as read ports or write ports mapped into the
PD6722 register set.
Configuring a GPSTB pin as a read port allows an easy way to read additional card status such as
VS1# and VS2# levels, a card socket microswitch status, a card port cover microswitch status, card
eject solenoid position status, or general system signal status.
Configuring a GPSTB pin as a write port allows an easy way to control additional features such as
card-state LEDs, card mechanism solenoids, or motor eject mechanisms.
13.1
Control of GPSTB Pins
The Extension Control 2 register controls the GPSTB pins.
For the PD6722, the A_GPSTB pin is controlled by the Extension Control 2 register at Socket A
(index 2Fh, extended index 0Bh), and the B_GPSTB pin is controlled by the Extension Control 2
register at Socket B (index 6Fh, extended index 0Bh).
The following table summarizes how the GPSTB pins are configured and how data is accessed
from external ports created by using a GPSTB pin to control an external read or write port.
Table 18. Registers for Control and Data of GPSTB Pins
Pin Name
A_GPSTB (PD6722)
B_GPSTB (PD6722)
GPSTB Control Access
External Port Data Access
Set register 2E to 0Ah,
Set register 2E to 0Bh,
access Extension Control 2 register at 2F
access External Data register at 2F
Set register 6E to 0Bh,
access Extension Control 2 register at 6F
Set register 6E to 0Ah,
access External Data register at 6F
Programming the Extension Control 2 Register
There is one Extension Control 2 register per GPSTB pin. Each register has identical GPSTB
control bits, as follows. See also the description of this register in “Extension Control 2 (PD6722
only)” on page 83.
Register Name: Extension Control 2
Register Per: socket
Extended Index: 0Bh
Index: 2Fh and 6Fh
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Active-high
GPSTB
GPSTB on
IOW*
GPSTB on
IOR*
Totem-pole
GPSTB
Reserved
Reserved
RW:00
RW:0
RW:0
RW:0
RW:0
RW:00
Datasheet
91
INTEL [ INTEL ]
