ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
10.7.6
Extension Control 2 (PD6722 only)
Register Name: Extension Control 2
Index: 2Fh
Register Per: socket
Extended Index: 0Bh
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Active-high
GPSTB
GPSTB on
IOW*
GPSTB on
IOR*
Totem-pole
GPSTB
Reserved
RW:00
Reserved
RW:00
RW:0
RW:0
RW:0
RW:0
Bit 5 — Active-high GPSTB
0
1
GPSTB ouputs are active-low.
GPSTB ouputs are active-high.
Bit 4 — GPSTB on IOW* (PD6722 only)
0
1
A_GPSTB (PD6722) pins are used as voltage sense.
A_GPSTB (PD6722) pins are used to strobe I/O writes on SD[15:8].
Note that setting this bit forces the pull-ups on A_GPSTB (PD6722) to be off, independent of the
setting of the Pull-Up Control bit (index 2Fh, extended index 03h, bit 5). See “External Data
(PD6722 only, Socket A, Index 6Fh)” on page 82, “Using GPSTB Pins for External Port Control
(PD6722 only)” on page 91, and “VS1# and VS2# Voltage Detection” on page 95.
Bit 3 — GPSTB on IOR* (PD6722 only)
0
1
B_GPSTB (PD6722) pins (socket B) are used as voltage sense.
B_GPSTB (PD6722) pins are used to strobe I/O reads on SD[15:8].
Note that setting this bit forces the pull-ups on B_GPSTB (PD6722) to be off, independent of the
setting of the Pull-Up Control bit (index 6Fh, extended index 03h, bit 5). See “External Data
(PD6722 only, Socket A, Index 6Fh)”, “Using GPSTB Pins for External Port Control (PD6722
only)”, and “VS1# and VS2# Voltage Detection”.
Bit 2 — Totem-pole GPSTB
0
1
GPSTB ouputs are open-collector.
GPSTB ouputs are totem-pole.
When GPSTB outputs are totem-pole, their ‘high’ level is driven to the level of the +5V pin,
instead of high-impedance.
Datasheet
83
INTEL [ INTEL ]
