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SPD6722QCCE 参数 Datasheet PDF下载

SPD6722QCCE图片预览
型号: SPD6722QCCE
PDF下载: 下载PDF文件 查看货源
内容描述: ISA到PC卡( PCMCIA )控制器 [ISA-to-PC-Card (PCMCIA) Controllers]
分类和应用: 总线控制器微控制器和处理器PC
文件页数/大小: 138 页 / 837 K
品牌: INTEL [ INTEL ]
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PD6710/22 ISA-to-PC-Card (PCMCIA) Controllers  
11.0  
Timing Registers  
The following information about the timing registers is important:  
All timing registers take effect immediately and should only be changed when the FIFO is  
empty (see the FIFO Control register on FIFO Controlon page 72).  
Selection of Timing 0 or Timing 1 register sets is controlled by I/O Window Control, bit 3  
and/or bit 7 (see I/O Window Controlon page 58).  
11.1  
Setup Timing 01  
Register Name: Setup Timing 01  
Index: 3Ah, 3Dh  
Register Per: socket  
Register Compatibility Type: 365  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Setup Prescalar Select  
RW:00  
Setup Multiplier Value  
RW:000001  
There are two separate Setup Timing registers, each with identical fields. These registers are  
located at the following indexes:  
Index Setup Timing  
3Ah  
3Dh  
Setup Timing 0  
Setup Timing 1  
The Setup Timing register for each timing set controls how long a PC Card cycles command (that  
is, -OE, -WE, -IORD, -IOWR; see Table 2 on page 20) setup will be, in terms of the number of  
internal clock cycles.  
The overall command setup number of clocks S is programmed by selecting a 2-bit prescaling  
value (bits 7:6 of this register) representing weights of 1, 16, 256, or 8192, and then selecting a  
multiplier value (bits 5:0) to which that prescalar is multiplied to produce the overall command  
setup timing length according to the following formula:  
S = (Npres × Nval) + 1  
The value of S, representing the number of internal clock cycles for command setup, is then  
multiplied by the internal clocks period to determine the command setup time (see PC Card Bus  
Timing Calculationson page 109 for further discussion).  
Bits 5:0 Setup Multiplier Value  
This field indicates an integer value Nval from 0 to 63; it is combined with a prescalar value (bits  
7:6) to control the length of setup time before a command becomes active.  
84  
Datasheet