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SPD6722QCCE 参数 Datasheet PDF下载

SPD6722QCCE图片预览
型号: SPD6722QCCE
PDF下载: 下载PDF文件 查看货源
内容描述: ISA到PC卡( PCMCIA )控制器 [ISA-to-PC-Card (PCMCIA) Controllers]
分类和应用: 总线控制器微控制器和处理器PC
文件页数/大小: 138 页 / 837 K
品牌: INTEL [ INTEL ]
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ISA-to-PC-Card (PCMCIA) Controllers PD6710/22  
Bit 2 LED Activity Enable  
0
1
LED activity disabled.  
LED activity enabled.  
This bit allows the LED_OUT* pin to reflect any activity in the card. Whenever PC Card cycles are  
in process to or from a card in either socket, LED_OUT* will be active (low).  
Bit 5 Pull-up Control  
0
1
Pull-ups on CD2, CD1, A_GPSTB, and B_GPSTB (PD6722) are in use.  
Pull-ups on CD2, CD1, A_GPSTB, and B_GPSTB (PD6722) are turned off.  
This bit turns off the pull-ups on CD2, CD1, and A_GPSTB and B_GPSTB (PD6722). Turning off  
these pull-ups can be used in addition to Suspend mode to even further reduce power when cards  
are inserted but no card accessibility is required. Even though power may or may not still be  
applied, all pull-ups and their associated inputs will be disabled.  
Bit 7:6 DMA Enable (PD6722 only)  
On the PD6722, DMA Enable bits 6 and 7 enable the DMA operation of the PC Card socket. At  
reset these bits are set to 0, and this is non-DMA mode. If either or both of these bits is set, the  
socket is in DMA mode. The three codes that cause DMA mode also select the use of one of three  
pins for the active-low -DREQ input at the PC Card interface.  
Bit 7  
Bit 6  
Pin Used  
0
1
1
1
0
1
-INPACK  
WP/-IOIS16  
BVD2/-SPKR  
For cards requiring DMA services but also needing input acknowledge functionality, or needing to  
indicate the size of I/O registers within a window, or needing digital speaker or LED operation, the  
selection of the -DREQ signal to the socket is made to be as flexible as possible.  
10.7.3  
Maximum DMA Acknowledge Delay (PD6722 only)  
Register Name: Maximum DMA  
Acknowledge Delay  
Register Per: socket  
Register Compatibility Type: ext.  
Extended Index: 04h  
Bit 4 Bit 3  
Index: 2Fh  
Bit 7  
Bit 6  
Bit 5  
Bit 2  
Bit 1  
Bit 0  
Maximum DMA Acknowledge Delay  
RW:00000000  
Datasheet  
79  
 
 
 
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