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SPD6722QCCE 参数 Datasheet PDF下载

SPD6722QCCE图片预览
型号: SPD6722QCCE
PDF下载: 下载PDF文件 查看货源
内容描述: ISA到PC卡( PCMCIA )控制器 [ISA-to-PC-Card (PCMCIA) Controllers]
分类和应用: 总线控制器微控制器和处理器PC
文件页数/大小: 138 页 / 837 K
品牌: INTEL [ INTEL ]
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ISA-to-PC-Card (PCMCIA) Controllers PD6710/22  
Bit 4 I/O Window 1 Size  
0
1
8-bit data path to I/O Window 1.  
16-bit data path to I/O Window 1.  
When bit 5 below is 0, this bit determines the size of the data path to I/O Window 1. When bit 5 is  
1, this bit is ignored.  
Bit 5 Auto-Size I/O Window 1  
0
1
I/O Window 1 Size (see bit 4) determines the data path to I/O Window 1.  
The data path to I/O Window 1 will be determined based on -IOIS16 returned by the card.  
This bit determines the width of the data path to I/O Window 1. Note that when this bit is 1, the  
-IOIS16 signal (see Table 2 on page 20) determines the window size. This bit must be set for  
proper ATA mode operation (see ATA Mode Operationon page 88).  
Bit 7 Timing Register Select 1  
0
1
Accesses made with timing specified in Timing Set 0.  
Accesses made with timing specified in Timing Set 1.  
This bit determines the access timing specification for I/O Window 1 (see Setup Timing 01on  
page 84).  
8.2  
System I/O Map 01 Start Address Low  
Register Name: System I/O Map 01 Start Address Low  
Index: 08h, 0Ch  
Register Per: socket  
Register Compatibility Type: 365  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Start Address 7:0  
RW:00000000  
There are two separate System I/O Map Start Address Low registers, each with identical fields.  
These registers are located at the following indexes:  
Index System I/O Map Start Address Low  
8h  
Ch  
System I/O Map 0 Start Address Low  
System I/O Map 1 Start Address Low  
Datasheet  
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