PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Bit 0 — Memory Map 0 Enable
0
1
Memory Mapping registers for Memory Space 0 disabled.
Memory Mapping registers for Memory Space 0 enabled.
When this bit is ‘1’, the Memory Mapping registers for Memory Space 0 will be enabled and the
controller will respond to memory accesses in the memory space defined by those registers.
Bit 1 — Memory Map 1 Enable
0
1
Memory Mapping registers for Memory Space 1 disabled.
Memory Mapping registers for Memory Space 1 enabled.
When this bit is ‘1’, the Memory Mapping registers for Memory Space 1 will be enabled and the
controller will respond to memory accesses in the memory space defined by those registers.
Bit 2 — Memory Map 2 Enable
0
1
Memory Mapping registers for Memory Space 2 disabled.
Memory Mapping registers for Memory Space 2 enabled.
When this bit is ‘1’, the Memory Mapping registers for Memory Space 2 will be enabled and the
controller will respond to memory accesses in the memory space defined by those registers.
Bit 3 — Memory Map 3 Enable
0
1
Memory Mapping registers for Memory Space 3 disabled.
Memory Mapping registers for Memory Space 3 enabled.
When this bit is ‘1’, the Memory Mapping registers for Memory Space 3 will be enabled and the
controller will respond to memory accesses in the memory space defined by those registers.
Bit 4 — Memory Map 4 Enable
0
1
Memory Mapping registers for Memory Space 4 disabled.
Memory Mapping registers for Memory Space 4 enabled.
When this bit is ‘1’, the Memory Mapping registers for Memory Space 4 will be enabled and the
controller will respond to memory accesses in the memory space defined by those registers.
Bit 5 — MEMCS16 Full Decode
This bit is not used. All addresses are used to determine the level of MEMCS16*.
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Datasheet
INTEL [ INTEL ]
